KR100962312B1 - 집적 회로의 컨택 사이즈들의 사이즈를 정함으로써 멀티레벨 컨택들을 제조하는 방법 - Google Patents

집적 회로의 컨택 사이즈들의 사이즈를 정함으로써 멀티레벨 컨택들을 제조하는 방법 Download PDF

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KR100962312B1
KR100962312B1 KR1020057001937A KR20057001937A KR100962312B1 KR 100962312 B1 KR100962312 B1 KR 100962312B1 KR 1020057001937 A KR1020057001937 A KR 1020057001937A KR 20057001937 A KR20057001937 A KR 20057001937A KR 100962312 B1 KR100962312 B1 KR 100962312B1
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opening
etching
openings
depth
delay
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KR20050039840A (ko
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케이 헬리그
매서드 암니퍼
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020057001937A 2002-08-02 2003-07-09 집적 회로의 컨택 사이즈들의 사이즈를 정함으로써 멀티레벨 컨택들을 제조하는 방법 Expired - Lifetime KR100962312B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/210,995 2002-08-02
US10/210,995 US6828240B2 (en) 2002-08-02 2002-08-02 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits

Publications (2)

Publication Number Publication Date
KR20050039840A KR20050039840A (ko) 2005-04-29
KR100962312B1 true KR100962312B1 (ko) 2010-06-10

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KR1020057001937A Expired - Lifetime KR100962312B1 (ko) 2002-08-02 2003-07-09 집적 회로의 컨택 사이즈들의 사이즈를 정함으로써 멀티레벨 컨택들을 제조하는 방법

Country Status (8)

Country Link
US (1) US6828240B2 (enExample)
EP (1) EP1525612A1 (enExample)
JP (1) JP4936665B2 (enExample)
KR (1) KR100962312B1 (enExample)
CN (1) CN100413050C (enExample)
AU (1) AU2003256458A1 (enExample)
TW (1) TWI308374B (enExample)
WO (1) WO2004013908A1 (enExample)

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US7470630B1 (en) * 2005-04-14 2008-12-30 Altera Corporation Approach to reduce parasitic capacitance from dummy fill
US7838203B1 (en) 2006-11-13 2010-11-23 National Semiconductor Corporation System and method for providing process compliant layout optimization using optical proximity correction to improve CMOS compatible non volatile memory retention reliability
US20080113483A1 (en) * 2006-11-15 2008-05-15 Micron Technology, Inc. Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures
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US7855146B1 (en) 2007-09-18 2010-12-21 National Semiconductor Corporation Photo-focus modulation method for forming transistor gates and related transistor devices
US20090221144A1 (en) * 2008-03-03 2009-09-03 National Applied Research Laboratories Manufacturing method for nano scale Ge metal structure
US7790491B1 (en) 2008-05-07 2010-09-07 National Semiconductor Corporation Method for forming non-volatile memory cells and related apparatus and system
US7786017B1 (en) 2009-09-17 2010-08-31 International Business Machines Corporation Utilizing inverse reactive ion etching lag in double patterning contact formation
US9343463B2 (en) * 2009-09-29 2016-05-17 Headway Technologies, Inc. Method of high density memory fabrication
US8227339B2 (en) * 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths
US8736069B2 (en) 2012-08-23 2014-05-27 Macronix International Co., Ltd. Multi-level vertical plug formation with stop layers of increasing thicknesses
US8987914B2 (en) 2013-02-07 2015-03-24 Macronix International Co., Ltd. Conductor structure and method
US9214351B2 (en) 2013-03-12 2015-12-15 Macronix International Co., Ltd. Memory architecture of thin film 3D array
US8993429B2 (en) 2013-03-12 2015-03-31 Macronix International Co., Ltd. Interlayer conductor structure and method
US9117526B2 (en) 2013-07-08 2015-08-25 Macronix International Co., Ltd. Substrate connection of three dimensional NAND for improving erase performance
US9070447B2 (en) 2013-09-26 2015-06-30 Macronix International Co., Ltd. Contact structure and forming method
US8970040B1 (en) 2013-09-26 2015-03-03 Macronix International Co., Ltd. Contact structure and forming method
US9343322B2 (en) 2014-01-17 2016-05-17 Macronix International Co., Ltd. Three dimensional stacking memory film structure
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9721964B2 (en) 2014-06-05 2017-08-01 Macronix International Co., Ltd. Low dielectric constant insulating material in 3D memory
US9356040B2 (en) 2014-06-27 2016-05-31 Macronix International Co., Ltd. Junction formation for vertical gate 3D NAND memory
TWI566365B (zh) * 2014-07-07 2017-01-11 旺宏電子股份有限公司 接觸結構及形成方法以及應用其之回路
US9379129B1 (en) 2015-04-13 2016-06-28 Macronix International Co., Ltd. Assist gate structures for three-dimensional (3D) vertical gate array memory structure
US9478259B1 (en) 2015-05-05 2016-10-25 Macronix International Co., Ltd. 3D voltage switching transistors for 3D vertical gate memory array
US9425209B1 (en) 2015-09-04 2016-08-23 Macronix International Co., Ltd. Multilayer 3-D structure with mirror image landing regions
US20170213885A1 (en) * 2016-01-21 2017-07-27 Micron Technology, Inc. Semiconductor structure and fabricating method thereof
US11031279B2 (en) * 2016-12-14 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with reduced trench loading effect
DE102018122473B4 (de) * 2017-09-29 2025-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Herstellungsverfahren für eine Halbleitervorrichtung
US10571758B2 (en) * 2018-01-05 2020-02-25 Innolux Corporation Display device
CN110970297B (zh) * 2018-09-29 2024-06-07 长鑫存储技术有限公司 补偿性蚀刻方法及结构、半导体器件及其制备方法
KR102783919B1 (ko) 2019-03-19 2025-03-24 삼성전자주식회사 반도체 소자
CN110767629B (zh) * 2019-10-30 2021-07-06 中国科学院微电子研究所 用于测量不同材料的蚀刻选择比的结构及方法
US11600628B2 (en) * 2020-01-15 2023-03-07 Globalfoundries U.S. Inc. Floating gate memory cell and memory array structure
WO2023028825A1 (zh) * 2021-08-31 2023-03-09 长江存储科技有限责任公司 一种半导体器件及其制备方法

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US20020055244A1 (en) * 2000-10-31 2002-05-09 Gert Burbach Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer

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US20020055244A1 (en) * 2000-10-31 2002-05-09 Gert Burbach Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer

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AU2003256458A1 (en) 2004-02-23
EP1525612A1 (en) 2005-04-27
TWI308374B (en) 2009-04-01
KR20050039840A (ko) 2005-04-29
WO2004013908A1 (en) 2004-02-12
US20040023499A1 (en) 2004-02-05
JP4936665B2 (ja) 2012-05-23
TW200402832A (en) 2004-02-16
CN100413050C (zh) 2008-08-20
CN1672256A (zh) 2005-09-21
US6828240B2 (en) 2004-12-07
JP2005535124A (ja) 2005-11-17

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