US9343463B2 - Method of high density memory fabrication - Google Patents
Method of high density memory fabrication Download PDFInfo
- Publication number
- US9343463B2 US9343463B2 US12/586,900 US58690009A US9343463B2 US 9343463 B2 US9343463 B2 US 9343463B2 US 58690009 A US58690009 A US 58690009A US 9343463 B2 US9343463 B2 US 9343463B2
- Authority
- US
- United States
- Prior art keywords
- level
- vias
- active
- dummy
- cmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000000034 method Methods 0.000 title abstract description 36
- 238000004519 manufacturing process Methods 0.000 title description 28
- 239000000872 buffer Substances 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000003491 array Methods 0.000 claims description 2
- 238000009826 distribution Methods 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 23
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 230000010354 integration Effects 0.000 abstract description 7
- 238000000059 patterning Methods 0.000 abstract description 6
- 230000000295 complement effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000004020 conductor Substances 0.000 description 10
- 238000000151 deposition Methods 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012464 large buffer Substances 0.000 description 2
- 230000005415 magnetization Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000002772 conduction electron Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H01L27/228—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
Definitions
- This invention relates generally to the fabrication of memory arrays.
- the invention relates to a method of forming a highly planar surface through whose use the process of integrating CMOS metal layers and memory junction layers will be improved.
- the memory junction layer (the layer containing the memory devices) to a CMOS metal layer below it.
- the critical junction layer of non-volatile memory is normally placed above many metal layers. Depending upon the particular circuit design, there is at least one and perhaps as many as five layers of metal below the memory junction layer.
- New memory types such as field induced MRAM (external magnetic fields used to change device magnetizations) and spin torque transfer memory (device magnetizations changed by the torque of conduction electrons) require the critical junction layer to be processed at the back-end of the line due to the anneal temperature limitation.
- the signal budget is very tight for any production-worthy processes.
- the requirement for CD budget for the junction layer is very tight across a device array ( ⁇ 2.0% 1 s). To achieve this kind of CD control, it will require a super-flat under-layer surface for the junction layer to be built upon.
- FIG. 1 a there is shown schematically an overhead view of an exemplary layout ( 100 ) of metal (conducting) lines ( 10 ), and metal studs ( 20 ), surrounded by dielectric layers ( 210 ), that would typically be presented as the uppermost surface of a lower CMOS integrated circuit level.
- the studs provide the prepared sites for making the required interconnections between the CMOS circuit level and individual memory cell devices to be formed in a device level above the CMOS level.
- these studs may also be denoted as “connection pads”, which denote the same type of structures at which connections between CMOS circuitry and active devices are to be made. It is the task of circuit integration to fabricate the additional levels of active device circuitry on this CMOS level layout so that the additional levels of active circuitry are properly integrated with the CMOS circuitry through contact to the CMOS studs and connection pads.
- FIG. 1 b is a schematic view of a cross-sectional cut through the circuit of FIG. 1 a through the horizontal line labeled 1 b .
- the cut provides a cross-sectional view of the two lines ( 10 ), two of the studs ( 20 ) and the dielectric material ( 210 ) surrounding them. It is understood that there may be many more CMOS levels beneath this level, but for the purposes of describing the invention herein, it is only necessary to deal with that portion of the CMOS level that is in immediate contact with the device level formed above it.
- FIG. 2 a there is shown an overhead schematic view of a more realistic prior art layout of CMOS lines and studs (shown below in FIG. 2 b ) on which has been indicated an array of twelve exemplary “objects,” presented as four columns of three objects in a column.
- This circuit is similar to that in FIG. 1 a , but it has these additional objects that include the active devices and non-active elements that are used to improve the structural qualities of the circuit.
- this circuit includes the deposition and patterning of buffer layers ( 60 ) of conducting material that are formed over the Cu material (( 10 ), and ( 20 ) in FIG. 2 b ) of the CMOS level.
- the buffer layers are for the purpose of preventing diffusion of Cu into the device level and to present a smooth surface on which to form the devices. All devices will be formed on these buffer layers.
- Objects A, B, G, H and I that are shown as ellipses with large X's drawn within them, are actually not physical objects, but are regions where devices could be placed to improve the integrity of the circuit, but are not so placed.
- Objects (A and B) and (G, H and I) are positioned, respectively, on rectangular buffer layers ( 60 ) formed contiguously over Cu wiring ( 10 ) and ( 11 ) in the CMOS level that are shown in FIG. 2 b .
- (C, D, E, F) and (J, K and L) are positioned over (shaded) dielectric regions ( 210 ) in the CMOS level. There is no large buffer layer formed contiguously over these dielectric regions, rather small individual circular buffer layers ( 60 ), shown as annular regions, are formed beneath junction devices of smaller radii.
- E, F, J and K label real studs that connect to the CMOS level. They are covered with circular patterned buffer layers ( 60 ) shown as small annular regions extending beyond the circular peripheries of junction devices ( 50 ) that are formed on these buffer layers. Junction devices formed on the real studs E, F, J and K are “active” junctions because they are electrically connected to the studs in the CMOS level. C, D and L are real junctions that are formed on circular buffer layers, but, in this exemplary circuit, there are no studs beneath them. These junctions are, therefore, called “dummy” junctions, because they have no electrical activity. They are formed to provide structural stability to the circuit.
- Dummy junctions are drawn with dashed circular peripheries to indicate their lack of activity. For performance purposes, we are supposing that active devices are not needed at locations A, B, G, H and I. For structural purposes, however, it would be desirable to form them there. Unfortunately, if they were formed there, they would be rendered active by contact with the Cu wiring beneath them, so they are “not allowed,” and are not formed.
- a “dummy” stud is a region in the CMOS level over which a memory junction is formed but under which there is no actual stud. Thus, the memory junction is fully formed, but does not act because it is electrically isolated from elements in the CMOS level.
- the non-existent dummy stud is shown as an annular region ( 30 ) drawn with a dashed line around a memory junction ( 70 ), also drawn with a dashed outline to indicate its inactivity.
- Each stud, active and dummy has a memory junction (or other like device) formed upon it.
- the memory junction is not formed directly on the stud, but is formed on a buffer layer that is deposited on the stud to control diffusion from the Cu forming the stud into the devices formed on the stud. These buffer layers are deposited and patterned and the devices are formed on them. The buffer layer formation will be discussed more fully below.
- the memory junction is formed in the upper device layer that is integrated with the lower CMOS layer.
- the active studs have active junctions ( 50 ), formed on them.
- the dummy studs have dummy (inactive) junctions ( 70 ) formed on them.
- Dummy studs (A, B, G, H, I) and inactive devices on them are not allowed in regions where there is already a Cu line beneath a buffer layer, as lines ( 10 ) and ( 11 ).
- the fabrication of the studs includes the formation of a buffer conduction layer ( 60 ) that both prevents Cu diffusion into the surrounding materials and facilitates the smooth deposition of the memory junction layers to be formed in the upper device level.
- This second role of the buffer layer is required because the upper surface of the Cu conduction line deposition is typically too rough for effective formation of a memory device directly upon it.
- the nature of this fabrication is such that buffer layers may be formed in different sizes, such as the large rectangular layer beneath A, B, G, H and I and the smaller circular layers beneath E and K. It is difficult to smoothly pattern buffer layers in different sizes and designs and, in addition, large regions of buffer layer are prone to peeling during annealing.
- FIG. 2 b there is shown a cross-sectional cut through the dashed line labeled 2 b in FIG. 2 a , showing two of the active memory junctions ( 50 ) formed on the buffered conduction layer ( 60 ) and contacting the active studs ( 20 ).
- FIG. 3 a there is shown a schematic overhead view of another prior art fabrication and, in FIG. 3 b , there is shown a schematic side view of a vertical cut through the line labeled 3 b of the fabrication in FIG. 3 a .
- the overhead view in 3 a shows the buffer layers ( 60 ) and active ( 50 ) and dummy ( 70 ) devices. Note that the dummy devices are drawn with broken line peripheries to more clearly indicate that they are not connected to any electrical portions of the CMOS layer.
- the device level which may be called a via connection layer (VAC layer) includes dielectric material depositions ( 215 ) formed over an etch-stop layer ( 95 ) that caps the CMOS level.
- VAC layer via connection layer
- the active devices are formed on a buffer layer ( 60 ) and are connected to the CMOS level through vias ( 80 ), formed as part of this via connection layer.
- the dummy devices are left unconnected to the lower CMOS level and are now separated from the lower level by the thickness of the dielectric layer ( 215 ).
- these dummy devices are allowed, unlike the dummy devices in FIG. 2 a that were not allowed (A, B, G, H and I in FIG. 2 a ).
- FIG. 3 a also has integration difficulties associated with it, particularly a difficulty in fabricating a flat, smooth VAC layer without properly filled dummy patterns and a difficulty in patterning a flat/smooth buffer layer due to the VAC underlayer.
- Inoh et al. U.S. Pat. No. 7,009,273 discloses a dummy pattern formed at the ends of a DRAM array so that photolithograpy or etching processes will not vary.
- a first object of this invention is to provide an integration scheme for the integration of a CMOS level and a device level.
- a second object of this invention is to provide such a scheme where there is an improved solution of problems associated with the metal layer connections between the CMOS level and the device level, particularly interfacial flatness between the two levels and difficulties in producing buffer layer patterns of different sizes.
- a third object of the present invention is to provide an integration scheme that relaxes pattern size and distribution constraints on the CMOS metal layer layout.
- a fourth object of the present invention is to provide such a method where the devices are memory junction (MRAM) devices.
- MRAM memory junction
- a fifth object of the present invention is to provide such a scheme that improves the memory junction layer CD control.
- the resulting device junction layer will have a layout including a segmented memory array surrounded by dummy devices that are formed on uniformly patterned buffer layers.
- the device junction layer will be constructed using a double pattern process that forms an evenly distributed array and dummy patterns for the super-flat layer process without limiting the under-metal layout.
- FIG. 1 a and FIG. 1 b are schematic illustrations of an overhead and side view of a prior art CMOS/device layer interface.
- FIG. 2 a and FIG. 2 b are schematic illustrations of an overhead and side view of an alternative prior art CMOS/device layer interface showing the effect of dummy devices and buffer layer constructions.
- FIG. 3 a and FIG. 3 b are schematic illustrations of an overhead and side view of an alternative prior art CMOS/device layer interface showing the effect of dummy devices and buffer layer constructions.
- FIG. 4 a , FIG. 4 b and FIG. 4 c are schematic illustrations of a common overhead ( 4 a ) and two side views ( 4 b ) ( 4 c ) of two embodiments of the present invention.
- FIG. 5 a - FIG. 5 d are a sequence of schematic illustrations of a method of fabricating the embodiment of FIG. 4 a and FIG. 4 b.
- FIG. 6 a - FIG. 6 d are a sequence of schematic views of a method of fabricating the embodiment of FIG. 4 a and FIG. 4 c.
- the preferred embodiments of the present invention are two methods of integrating a CMOS level and an active device level, which in these embodiments is a memory device level, across a super-flat intermediate surface.
- the method is to split the formation of active interconnecting vias and dummy non-interconnecting vias into two different mask patterning steps.
- the etch that forms dummy vias will be stopped at one of two possible etch-stop layers formed above the lower CMOS metal layers while the etch to form the active interconnecting vias will penetrate the etch stop layer over the CMOS level and electrically connect to the metal layers below.
- FIG. 4 a there is shown a schematic overhead view of a complete fabrication, similar in this overhead view to that in FIG. 3 a , but formed in accord with the methods of the present invention.
- the array of junctions includes active junction devices ( 50 ) and the dummy junction devices ( 70 ) (drawn with dashed circular peripheries).
- the uniform array of active and dummy junctions and vias connecting them to the CMOS level when formed in the method described below, will provide a super-flat interface between the CMOS and device level and achieve the objects of the present invention.
- FIG. 4 b there is shown a side cross-sectional view taken through line 4 b of FIG. 4 a to illustrate a first embodiment of the present inventive scheme.
- the lower CMOS level ( 100 ) is capped with an etch-stop layer ( 95 ) which is a layer of SiN formed to a thickness between approximately 30 and 150 nm.
- An upper device level ( 200 ) including active ( 50 ) and dummy ( 70 ) devices, is formed over the CMOS level and separated from it by a dielectric layer ( 215 ) that can be a layer of SiO 2 formed to a thickness between approximately 50 nm and 500 nm.
- the CMOS level ( 100 ) includes conducting connection pads ( 20 ) to which active interconnecting vias ( 80 ) are electrically connected. These active vias ( 80 ) are filled with conducting material and pass through the etch-stop layer ( 95 ) to complete the electrical connection to the connection pads ( 20 ). On the upper surface of the fabrication, these vias are covered by buffer layers ( 60 ) on which the active devices ( 50 ) are formed.
- the fabrication also includes dummy vias ( 85 ) that are also filled with conducting material, but these dummy vias are not electrically connected to any metal or connection pads in the CMOS layer because they have been stopped by the etch-stop layer ( 95 ).
- the result of this fabrication is that the dummy vias are “dummy” only in the sense that they fail to complete an interconnection with any conducting elements in the CMOS level because they do not penetrate etch stop layer ( 95 ), but they function structurally as active vias in that they are filled with conducting material and populate the device level uniformly.
- FIG. 4 c there is shown an alternative embodiment of the present invention, also fabricating the structure shown in FIG. 4 a , but using a different scheme.
- FIG. 4 c shows a cross-section of FIG. 4 a taken through line 4 b .
- the upper device level ( 200 ) which is formed on a first etch-stop layer ( 95 ) over CMOS level ( 100 ), now includes two dielectric layers ( 215 ) and ( 220 ), separated from each other by a second etch-stop layer ( 195 ).
- Both dielectric layers can be layers of SiO 2 formed to a thickness between approximately 50 and 500 nm in this embodiment and the two etch stop layers can be layers of SiN formed to a thickness between approximately 30 and 150 nm.
- the dummy vias ( 85 ) are stopped at the second etch stop layer, while the active vias ( 80 ) pass through both the first and second etch stop layers. It is noted that the thickness of the etch stop layer can determine whether the etch passes through one or both layers.
- FIGS. 5 a -5 d and FIGS. 6 a -6 d will illustrate, respectively, the methods by which the circuit fabrications of FIG. 4 b and FIG. 4 c can be formed.
- CMOS level 100 on which an etch stop layer ( 95 ) has been formed.
- the etch-stop layer can be a layer of SiN formed to a thickness of between approximately 30 nm and 150 nm.
- the CMOS level contains dielectric material ( 210 ), such as SiO 2 , various metal connection pads ( 20 ) and conducting lines ( 10 ) to which connections will ultimately be made to an upper device level yet to be fabricated.
- This dielectric layer can be a layer of SiO 2 formed to a thickness between approximately 50 nm and 500 nm.
- a first pattern and etch process etches via trenches for the active vias ( 80 ) through both the dielectric layer ( 215 ) and the etch-stop layer ( 95 ) to expose the connection pads ( 20 ).
- This first etch is a dry etch.
- FIG. 5 c there is shown a second pattern and etch process that defines the dummy vias ( 85 ). This process penetrates the dielectric layer ( 215 ), but stops at the etch stop layer ( 95 ). After this second etch, the active and dummy via holes are both filled with conductive material. The active via trenches, having exposed the connecting pads, allow the fill of conductive material to electrically contact the connection pads. The layer now has a stiffness and mechanical integrity resulting from the array of filled vias.
- FIG. 5 d there is shown schematically that the upper surface of the fabrication of FIG. 5 c has been planarized, by a CMP process (chemical mechanical polishing process) to remove any excess conductor from the via fills that might overflow onto the upper surface.
- Layers of conducting buffer material ( 60 ) are now formed over the upper surface of the fabrication. These layers are normally formed by first depositing a completely covering metal layer, then patterning the layer to surround the vias using a photo/etching process and filling the spaces between the resulting strips of buffer with a dielectric layer which is then planarized.
- active ( 50 ) and dummy ( 70 ) memory junction devices are formed over the patterned buffer material that covers each via. We will not describe the processes by which the junction devices are fabricated as they are known in the art.
- FIG. 6 a there is shown the first process step in the formation of the fabrication illustrated in FIG. 4 c .
- a first blanket dielectric layer ( 215 ) is formed on the first etch-stop layer.
- the first etch-stop layer is a layer of SiN formed to a thickness of between 30 and 150 nm.
- the first blanket dielectric layer is a layer of SiO 2 formed to a thickness between approximately 30 and 150 nm.
- FIG. 6 b there is shown schematically the fabrication of FIG. 6 a where a second etch-stop layer ( 195 ) has been formed over the first dielectric layer ( 215 ) and a second dielectric layer ( 220 ) is formed over the second etch-stop layer.
- a second etch-stop layer 195
- a second dielectric layer 220
- These layers are substantially identical with the first etch stop and blanket dielectric layers.
- FIG. 6 c there is shown schematically the fabrication of FIG. 6 b wherein a first pattern and etch process creates via trenches ( 80 ) that pass through both dielectric layers ( 220 ), ( 215 ) and both etch-stop layers ( 195 ), ( 95 ) and form openings to expose connecting pads ( 20 ) in the CMOS level.
- This is a dry etch process that is known in the art.
- FIG. 6 d there is shown schematically the fabrication of FIG. 6 c where a second pattern and etch process forms openings for the dummy vias ( 85 ) by passing through only the second dielectric layer ( 220 ) and stopping at (or passing through) the second etch-stop layer ( 195 ).
- the etched openings of both active and dummy vias are now filled with a conducting material.
- the conducting material in the active via trenches electrically contacts the connecting pads.
- the fabrication is then planarized, by a CMP process (chemical mechanical process) on the surface of the second dielectric layer to remove any excess conductor overflowing from the via fills.
- a layer of conducting buffer material ( 60 ) is formed over the entire fabrication.
- a pattern and etch process defines buffer layer strips ( 60 ) and a dielectric layer refills the spaces between the strips.
- the resulting fabrication is then planarized.
- memory junction devices are formed over the buffer layer covering each via.
- Devices ( 50 ) are active and are conductively connected to the CMOS layer.
- Devices ( 70 ) are dummy and do not connect to the CMOS level. We will not describe the processes by which the junction devices are fabricated as they are known in the art.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (4)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/586,900 US9343463B2 (en) | 2009-09-29 | 2009-09-29 | Method of high density memory fabrication |
PCT/US2010/002615 WO2011040953A1 (en) | 2009-09-29 | 2010-09-24 | Method of high density memory fabrication |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/586,900 US9343463B2 (en) | 2009-09-29 | 2009-09-29 | Method of high density memory fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
US20110073917A1 US20110073917A1 (en) | 2011-03-31 |
US9343463B2 true US9343463B2 (en) | 2016-05-17 |
Family
ID=43779322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/586,900 Active 2030-10-27 US9343463B2 (en) | 2009-09-29 | 2009-09-29 | Method of high density memory fabrication |
Country Status (2)
Country | Link |
---|---|
US (1) | US9343463B2 (en) |
WO (1) | WO2011040953A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200152571A1 (en) * | 2017-08-29 | 2020-05-14 | Micron Technology, Inc. | Integrated Assemblies |
US10923420B2 (en) | 2017-08-11 | 2021-02-16 | Samsung Electronics Co., Ltd. | Semiconductor device including dummy contact |
US10964751B2 (en) | 2019-01-17 | 2021-03-30 | Samsung Electronics Co., Ltd. | Semiconductor device having plural dummy memory cells |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8779553B2 (en) | 2011-06-16 | 2014-07-15 | Xilinx, Inc. | Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone |
US8560982B2 (en) * | 2011-06-27 | 2013-10-15 | Xilinx, Inc. | Integrated circuit design using through silicon vias |
US8524511B1 (en) | 2012-08-10 | 2013-09-03 | Headway Technologies, Inc. | Method to connect a magnetic device to a CMOS transistor |
US9793089B2 (en) | 2013-09-16 | 2017-10-17 | Kla-Tencor Corporation | Electron emitter device with integrated multi-pole electrode structure |
US20150076697A1 (en) * | 2013-09-17 | 2015-03-19 | Kla-Tencor Corporation | Dummy barrier layer features for patterning of sparsely distributed metal features on the barrier with cmp |
KR102212556B1 (en) * | 2014-10-08 | 2021-02-08 | 삼성전자주식회사 | Semiconductor device |
KR102435524B1 (en) * | 2015-10-21 | 2022-08-23 | 삼성전자주식회사 | Semiconductor memory device |
CN112768601B (en) * | 2019-11-04 | 2023-11-24 | 联华电子股份有限公司 | magnetoresistive random access memory |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5850366A (en) | 1997-07-24 | 1998-12-15 | Texas Instruments Incorporated | Memory array having dummy cells implemented using standard array cells |
US6380087B1 (en) | 2000-06-19 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | CMP process utilizing dummy plugs in damascene process |
US6828240B2 (en) | 2002-08-02 | 2004-12-07 | Advanced Micro Devices, Inc. | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
US20050026341A1 (en) * | 2003-07-28 | 2005-02-03 | Joachim Nuetzel | Method of forming isolation dummy fill structures |
US20050127519A1 (en) * | 2003-12-05 | 2005-06-16 | Matrix Semiconductor, Inc. | High density contact to relaxed geometry layers |
US7009273B2 (en) | 2002-09-19 | 2006-03-07 | Kabushiki Kaisha Toshiba | Semiconductor device with a cavity therein and a method of manufacturing the same |
US20080225576A1 (en) | 2007-03-15 | 2008-09-18 | Magic Technologies, Inc. | Method of magnetic tunneling junction pattern layout for magnetic random access memory |
US20090194768A1 (en) | 2002-08-08 | 2009-08-06 | Leedy Glenn J | Vertical system integration |
-
2009
- 2009-09-29 US US12/586,900 patent/US9343463B2/en active Active
-
2010
- 2010-09-24 WO PCT/US2010/002615 patent/WO2011040953A1/en active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5850366A (en) | 1997-07-24 | 1998-12-15 | Texas Instruments Incorporated | Memory array having dummy cells implemented using standard array cells |
US6380087B1 (en) | 2000-06-19 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | CMP process utilizing dummy plugs in damascene process |
US6828240B2 (en) | 2002-08-02 | 2004-12-07 | Advanced Micro Devices, Inc. | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
US20090194768A1 (en) | 2002-08-08 | 2009-08-06 | Leedy Glenn J | Vertical system integration |
US7009273B2 (en) | 2002-09-19 | 2006-03-07 | Kabushiki Kaisha Toshiba | Semiconductor device with a cavity therein and a method of manufacturing the same |
US20050026341A1 (en) * | 2003-07-28 | 2005-02-03 | Joachim Nuetzel | Method of forming isolation dummy fill structures |
US20050127519A1 (en) * | 2003-12-05 | 2005-06-16 | Matrix Semiconductor, Inc. | High density contact to relaxed geometry layers |
US20080225576A1 (en) | 2007-03-15 | 2008-09-18 | Magic Technologies, Inc. | Method of magnetic tunneling junction pattern layout for magnetic random access memory |
Non-Patent Citations (1)
Title |
---|
International Search Report PCT/US 10/02615 Mail date-Nov. 18, 2010, Magic Techologies, Inc. |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10923420B2 (en) | 2017-08-11 | 2021-02-16 | Samsung Electronics Co., Ltd. | Semiconductor device including dummy contact |
US20200152571A1 (en) * | 2017-08-29 | 2020-05-14 | Micron Technology, Inc. | Integrated Assemblies |
US11348871B2 (en) * | 2017-08-29 | 2022-05-31 | Micron Technology, Inc. | Integrated assemblies |
US10964751B2 (en) | 2019-01-17 | 2021-03-30 | Samsung Electronics Co., Ltd. | Semiconductor device having plural dummy memory cells |
Also Published As
Publication number | Publication date |
---|---|
WO2011040953A1 (en) | 2011-04-07 |
US20110073917A1 (en) | 2011-03-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9343463B2 (en) | Method of high density memory fabrication | |
US8772051B1 (en) | Fabrication method for embedded magnetic memory | |
US7508700B2 (en) | Method of magnetic tunneling junction pattern layout for magnetic random access memory | |
KR101266656B1 (en) | Semiconductor device and method of manufacturing the same | |
US7122386B1 (en) | Method of fabricating contact pad for magnetic random access memory | |
US12075630B2 (en) | Methods of forming magnetoresistive devices and integrated circuits | |
CN107644837A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
TW202115935A (en) | Magnetoresistive devices and methods of fabricating such devices | |
JPH04130664A (en) | Semiconductor device and manufacture thereof | |
US20130082382A1 (en) | Semiconductor device | |
CN107644838A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
US7804706B2 (en) | Bottom electrode mask design for ultra-thin interlayer dielectric approach in MRAM device fabrication | |
EP0564136B1 (en) | Method for planarization of an integrated circuit | |
JPH0685080A (en) | Semiconductor and its manufacture | |
CN107644841A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
US7919407B1 (en) | Method of high density field induced MRAM process | |
WO2021107970A1 (en) | Bonded assembly containing laterally bonded bonding pads and methods of forming the same | |
US20120112358A1 (en) | Stack-type semiconductor device and method for manufacturing the same | |
US11600578B2 (en) | Scribe structure for memory device | |
US8390129B2 (en) | Semiconductor device with a plurality of mark through substrate vias | |
JPH04320051A (en) | Interlayer contact structure of semiconductor layer and method therefor | |
US7005329B2 (en) | Method for manufacturing semiconductor device | |
US7341875B2 (en) | Semiconductor memory device with a capacitor formed therein and a method for forming the same | |
CN107644836A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
CN113035833B (en) | Multilayer wiring adapter plate and preparation method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MAGIC TECHNOLOGIES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHONG, TOM;ZHONG, ADAM;KAN, WAI-MING J.;AND OTHERS;REEL/FRAME:023554/0462 Effective date: 20090917 |
|
AS | Assignment |
Owner name: HEADWAY TECHNOLOGIES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MAGIC TECHNOLOGIES, INC.;REEL/FRAME:031929/0121 Effective date: 20131219 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEADWAY TECHNOLOGIES, INC.;REEL/FRAME:048692/0917 Effective date: 20190204 Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEADWAY TECHNOLOGIES, INC.;REEL/FRAME:048692/0917 Effective date: 20190204 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |