JP4936665B2 - 集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 - Google Patents
集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 Download PDFInfo
- Publication number
- JP4936665B2 JP4936665B2 JP2004526030A JP2004526030A JP4936665B2 JP 4936665 B2 JP4936665 B2 JP 4936665B2 JP 2004526030 A JP2004526030 A JP 2004526030A JP 2004526030 A JP2004526030 A JP 2004526030A JP 4936665 B2 JP4936665 B2 JP 4936665B2
- Authority
- JP
- Japan
- Prior art keywords
- opening
- etching
- depth
- contact
- lag
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Description
これらの利点は、添付した図面を参照して以下の詳細の説明を読むことによって、当業者にとって明らかになろう。
L=1−(Dmin/D) (方程式1)
ただし、 L=エッチングラグ;
Dmin=最小直径を有するコンタクトの深さ
D=異なる直径を有するコンタクトの深さ
上述のエッチングラグは、必ずしも直径と深さに線形であるとは限らない。
Loptimal=1−(CDshallow/CDDeep) (方程式2)
ただし、 Loptimal=最適なエッチングラグ
CDshallow=最も浅いコンタクトの深さ
CDDeep=最も深いコンタクトの深さ
Claims (2)
- 第1半導体基板上の半導体デバイス上の誘電材に、第1開口部を第1深さにエッチングし、前記第1半導体基板上の前記誘電材に第2開口部を第2深さにエッチングし、前記第1開口部及び前記第2開口部は、エッチングラグによって、エッチングが前記第1及び第2深さにほぼ同時に到達するように、それぞれサイズが異なるものとされ、前記第1開口部及び第2開口部を導電材で充填する、集積回路を形成するための方法であって、
前記第1開口部と同じとなるようサイジングされるキャリブレーション開口部を含む前記誘電材の複数の開口部をエッチングするステップと、
前記複数の開口部のエッチングから、複数の深さを測定し、かつ、前記複数の深さに対する前記キャリブレーション開口部比率を1から減算した値に等しくなるように複数エッチングラグを算出することによって、複数の開口部のエッチングラグを決定するステップと、
前記第2深さに対する前記第1深さの比率を1から減算した値を算出することによって、最適なエッチングラグを決定するステップと、
最適なエッチングラグに最も近似するエッチングラグを有する前記開口部の前記サイズに基づいて前記第2開口部をサイジングするステップとを含む、方法。 - 第1半導体基板上の半導体デバイス上の誘電材に、第1開口部を第1深さにエッチングし、前記第1半導体基板上の前記誘電材に第2開口部を第2深さにエッチングし、前記第1半導体基板の下の第2半導体基板表面上の誘電材に第3開口部を対応する第3深さにエッチングし、前記第1開口部、前記第2開口部、および前記第3開口部は、エッチングが対応する第1深さ、第2深さおよび第3深さにほぼ同時に到達するように異なるサイズとされ、前記第1開口部、前記第2開口部、前記第3開口部を導電材で充填する、集積回路を形成するための方法であって、
誘電材に、前記第1開口部と同じとなるようにサイズされるキャリブレーション開口部を含む複数の開口部をエッチングし、前記複数の深さを測定し、かつ、前記複数の深さに対する前記キャリブレーション開口部の深さ比率を1から減算した値と等しい値となるようにエッチングラグを算出することで、複数の開口部のエッチングラグを決定するステップと、
前記第2深さに対する前記第1深さの比率を算出することによって、第1最適エッチングラグを決定するステップと、
前記第3深さに対する前記第1深さの比率を1から減算した値を算出することによって、第2最適エッチングラグを決定するステップと、
前記第1最適エッチングラグに最も近似するエッチングラグを有する前記開口部の前記サイズに基づいて第2開口部をサイジングするステップと、
前記第3最適エッチングラグに最も近似するエッチングラグを有する前記開口部の前記サイズに基づいて第3開口部をサイジングするステップとを含む、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/210,995 US6828240B2 (en) | 2002-08-02 | 2002-08-02 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
US10/210,995 | 2002-08-02 | ||
PCT/US2003/021282 WO2004013908A1 (en) | 2002-08-02 | 2003-07-09 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005535124A JP2005535124A (ja) | 2005-11-17 |
JP2005535124A5 JP2005535124A5 (ja) | 2012-03-08 |
JP4936665B2 true JP4936665B2 (ja) | 2012-05-23 |
Family
ID=31187481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004526030A Expired - Lifetime JP4936665B2 (ja) | 2002-08-02 | 2003-07-09 | 集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6828240B2 (ja) |
EP (1) | EP1525612A1 (ja) |
JP (1) | JP4936665B2 (ja) |
KR (1) | KR100962312B1 (ja) |
CN (1) | CN100413050C (ja) |
AU (1) | AU2003256458A1 (ja) |
TW (1) | TWI308374B (ja) |
WO (1) | WO2004013908A1 (ja) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7504340B1 (en) * | 2004-06-14 | 2009-03-17 | National Semiconductor Corporation | System and method for providing contact etch selectivity using RIE lag dependence on contact aspect ratio |
US7232762B2 (en) * | 2004-06-16 | 2007-06-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved low power SRAM contact |
KR100614773B1 (ko) * | 2004-12-28 | 2006-08-22 | 삼성전자주식회사 | 화학 기계적 연마 방법 |
US7470630B1 (en) * | 2005-04-14 | 2008-12-30 | Altera Corporation | Approach to reduce parasitic capacitance from dummy fill |
US7838203B1 (en) | 2006-11-13 | 2010-11-23 | National Semiconductor Corporation | System and method for providing process compliant layout optimization using optical proximity correction to improve CMOS compatible non volatile memory retention reliability |
US20080113483A1 (en) * | 2006-11-15 | 2008-05-15 | Micron Technology, Inc. | Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures |
US7629255B2 (en) * | 2007-06-04 | 2009-12-08 | Lam Research Corporation | Method for reducing microloading in etching high aspect ratio structures |
US7855146B1 (en) | 2007-09-18 | 2010-12-21 | National Semiconductor Corporation | Photo-focus modulation method for forming transistor gates and related transistor devices |
US20090221144A1 (en) * | 2008-03-03 | 2009-09-03 | National Applied Research Laboratories | Manufacturing method for nano scale Ge metal structure |
US7790491B1 (en) | 2008-05-07 | 2010-09-07 | National Semiconductor Corporation | Method for forming non-volatile memory cells and related apparatus and system |
US7786017B1 (en) | 2009-09-17 | 2010-08-31 | International Business Machines Corporation | Utilizing inverse reactive ion etching lag in double patterning contact formation |
US9343463B2 (en) * | 2009-09-29 | 2016-05-17 | Headway Technologies, Inc. | Method of high density memory fabrication |
US8227339B2 (en) * | 2009-11-02 | 2012-07-24 | International Business Machines Corporation | Creation of vias and trenches with different depths |
US8736069B2 (en) | 2012-08-23 | 2014-05-27 | Macronix International Co., Ltd. | Multi-level vertical plug formation with stop layers of increasing thicknesses |
US8987914B2 (en) | 2013-02-07 | 2015-03-24 | Macronix International Co., Ltd. | Conductor structure and method |
US8993429B2 (en) | 2013-03-12 | 2015-03-31 | Macronix International Co., Ltd. | Interlayer conductor structure and method |
US9214351B2 (en) | 2013-03-12 | 2015-12-15 | Macronix International Co., Ltd. | Memory architecture of thin film 3D array |
US9117526B2 (en) | 2013-07-08 | 2015-08-25 | Macronix International Co., Ltd. | Substrate connection of three dimensional NAND for improving erase performance |
US9070447B2 (en) | 2013-09-26 | 2015-06-30 | Macronix International Co., Ltd. | Contact structure and forming method |
US8970040B1 (en) | 2013-09-26 | 2015-03-03 | Macronix International Co., Ltd. | Contact structure and forming method |
US9343322B2 (en) | 2014-01-17 | 2016-05-17 | Macronix International Co., Ltd. | Three dimensional stacking memory film structure |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9721964B2 (en) | 2014-06-05 | 2017-08-01 | Macronix International Co., Ltd. | Low dielectric constant insulating material in 3D memory |
US9356040B2 (en) | 2014-06-27 | 2016-05-31 | Macronix International Co., Ltd. | Junction formation for vertical gate 3D NAND memory |
TWI566365B (zh) * | 2014-07-07 | 2017-01-11 | 旺宏電子股份有限公司 | 接觸結構及形成方法以及應用其之回路 |
US9379129B1 (en) | 2015-04-13 | 2016-06-28 | Macronix International Co., Ltd. | Assist gate structures for three-dimensional (3D) vertical gate array memory structure |
US9478259B1 (en) | 2015-05-05 | 2016-10-25 | Macronix International Co., Ltd. | 3D voltage switching transistors for 3D vertical gate memory array |
US9425209B1 (en) | 2015-09-04 | 2016-08-23 | Macronix International Co., Ltd. | Multilayer 3-D structure with mirror image landing regions |
US20170213885A1 (en) * | 2016-01-21 | 2017-07-27 | Micron Technology, Inc. | Semiconductor structure and fabricating method thereof |
US11031279B2 (en) * | 2016-12-14 | 2021-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with reduced trench loading effect |
US10571758B2 (en) * | 2018-01-05 | 2020-02-25 | Innolux Corporation | Display device |
CN110970297A (zh) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | 补偿性蚀刻方法及结构、半导体器件及其制备方法 |
KR20200111857A (ko) | 2019-03-19 | 2020-10-05 | 삼성전자주식회사 | 반도체 소자 |
CN110767629B (zh) * | 2019-10-30 | 2021-07-06 | 中国科学院微电子研究所 | 用于测量不同材料的蚀刻选择比的结构及方法 |
US11600628B2 (en) * | 2020-01-15 | 2023-03-07 | Globalfoundries U.S. Inc. | Floating gate memory cell and memory array structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05315457A (ja) * | 1992-05-07 | 1993-11-26 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08316320A (ja) * | 1995-05-22 | 1996-11-29 | Nec Corp | 半導体装置の製造方法 |
JP2001044441A (ja) * | 1999-07-29 | 2001-02-16 | Sony Corp | 完全空乏soi型半導体装置及び集積回路 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05121369A (ja) | 1991-10-24 | 1993-05-18 | Oki Electric Ind Co Ltd | 半導体装置のコンタクトホールエツチング方法 |
JPH05267251A (ja) * | 1992-03-18 | 1993-10-15 | Oki Electric Ind Co Ltd | 半導体装置におけるコンタクトホールの形成方法 |
US5814547A (en) * | 1997-10-06 | 1998-09-29 | Industrial Technology Research Institute | Forming different depth trenches simultaneously by microloading effect |
KR100265596B1 (ko) * | 1997-10-27 | 2000-10-02 | 김영환 | 반도체 소자의 제조방법 |
US5994780A (en) * | 1997-12-16 | 1999-11-30 | Advanced Micro Devices, Inc. | Semiconductor device with multiple contact sizes |
US6207534B1 (en) * | 1999-09-03 | 2001-03-27 | Chartered Semiconductor Manufacturing Ltd. | Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing |
US6211059B1 (en) * | 1999-10-29 | 2001-04-03 | Nec Corporation | Method of manufacturing semiconductor device having contacts with different depths |
US6380087B1 (en) | 2000-06-19 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | CMP process utilizing dummy plugs in damascene process |
DE10054109C2 (de) * | 2000-10-31 | 2003-07-10 | Advanced Micro Devices Inc | Verfahren zum Bilden eines Substratkontakts in einem Feldeffekttransistor, der über einer vergrabenen Isolierschicht gebildet ist |
US6294423B1 (en) * | 2000-11-21 | 2001-09-25 | Infineon Technologies North America Corp. | Method for forming and filling isolation trenches |
US6566191B2 (en) * | 2000-12-05 | 2003-05-20 | International Business Machines Corporation | Forming electronic structures having dual dielectric thicknesses and the structure so formed |
-
2002
- 2002-08-02 US US10/210,995 patent/US6828240B2/en not_active Expired - Lifetime
-
2003
- 2003-07-09 KR KR1020057001937A patent/KR100962312B1/ko active IP Right Grant
- 2003-07-09 CN CNB038182572A patent/CN100413050C/zh not_active Expired - Lifetime
- 2003-07-09 AU AU2003256458A patent/AU2003256458A1/en not_active Abandoned
- 2003-07-09 EP EP03766843A patent/EP1525612A1/en not_active Withdrawn
- 2003-07-09 JP JP2004526030A patent/JP4936665B2/ja not_active Expired - Lifetime
- 2003-07-09 WO PCT/US2003/021282 patent/WO2004013908A1/en active Application Filing
- 2003-07-22 TW TW092119912A patent/TWI308374B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05315457A (ja) * | 1992-05-07 | 1993-11-26 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08316320A (ja) * | 1995-05-22 | 1996-11-29 | Nec Corp | 半導体装置の製造方法 |
JP2001044441A (ja) * | 1999-07-29 | 2001-02-16 | Sony Corp | 完全空乏soi型半導体装置及び集積回路 |
Also Published As
Publication number | Publication date |
---|---|
KR20050039840A (ko) | 2005-04-29 |
US20040023499A1 (en) | 2004-02-05 |
TWI308374B (en) | 2009-04-01 |
WO2004013908A1 (en) | 2004-02-12 |
CN100413050C (zh) | 2008-08-20 |
AU2003256458A1 (en) | 2004-02-23 |
EP1525612A1 (en) | 2005-04-27 |
JP2005535124A (ja) | 2005-11-17 |
CN1672256A (zh) | 2005-09-21 |
TW200402832A (en) | 2004-02-16 |
US6828240B2 (en) | 2004-12-07 |
KR100962312B1 (ko) | 2010-06-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4936665B2 (ja) | 集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 | |
JP4347637B2 (ja) | トレンチ側壁のバッファー層を使用して半導体装置用金属配線を形成する方法及びそれにより製造された装置 | |
US11594419B2 (en) | Reduction of line wiggling | |
US6444574B1 (en) | Method for forming stepped contact hole for semiconductor devices | |
US6495448B1 (en) | Dual damascene process | |
US20060292775A1 (en) | Method of manufacturing DRAM capable of avoiding bit line leakage | |
US5966632A (en) | Method of forming borderless metal to contact structure | |
JP2004014828A (ja) | 半導体装置の製造方法 | |
JP2007521630A (ja) | 集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 | |
JP3000935B2 (ja) | 半導体装置の製造方法 | |
CN1841698A (zh) | 用于制造半导体器件的方法 | |
TW200540969A (en) | Semiconductor device with partially recessed hard mask and method for contact etching thereof | |
US7648910B2 (en) | Method of manufacturing opening and via opening | |
US6664181B2 (en) | Method for fabricating semiconductor device | |
CN102339791A (zh) | 一种半导体器件制作方法 | |
JP4379245B2 (ja) | 半導体装置の製造方法 | |
CN102044471A (zh) | 互连结构及其形成方法 | |
US7326632B2 (en) | Method for fabricating metal wirings of semiconductor device | |
KR100791707B1 (ko) | 반도체 소자의 층간 절연막 평탄화 방법 | |
JP2004072107A (ja) | 変形されたデュアルダマシン工程を利用した半導体素子の金属配線形成方法 | |
KR100265828B1 (ko) | 반도체소자 제조방법 | |
KR100636983B1 (ko) | 금속층을 식각하는 방법 및 이 방법으로 제조된 반도체 소자 | |
KR20000019171A (ko) | 감광성 폴리머를 사용하는 금속배선 형성방법 | |
KR20040029219A (ko) | 반도체 소자의 제조 방법 | |
KR20020054683A (ko) | 반도체 소자의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060710 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060710 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100421 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100526 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100824 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100831 |
|
RD05 | Notification of revocation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7425 Effective date: 20100902 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100924 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20101001 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20101026 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20101102 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101125 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110914 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20111214 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20111221 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120116 |
|
A524 | Written submission of copy of amendment under article 19 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A524 Effective date: 20120119 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120123 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120208 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120221 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150302 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4936665 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |