WO2023028825A1 - 一种半导体器件及其制备方法 - Google Patents

一种半导体器件及其制备方法 Download PDF

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Publication number
WO2023028825A1
WO2023028825A1 PCT/CN2021/115613 CN2021115613W WO2023028825A1 WO 2023028825 A1 WO2023028825 A1 WO 2023028825A1 CN 2021115613 W CN2021115613 W CN 2021115613W WO 2023028825 A1 WO2023028825 A1 WO 2023028825A1
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Prior art keywords
isolation
substrate
device region
region
trench
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PCT/CN2021/115613
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English (en)
French (fr)
Inventor
侯会丹
姚兰
石艳伟
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长江存储科技有限责任公司
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Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to PCT/CN2021/115613 priority Critical patent/WO2023028825A1/zh
Priority to CN202180003480.5A priority patent/CN113906551A/zh
Priority to US17/854,477 priority patent/US20230063917A1/en
Priority to US17/857,965 priority patent/US20230067454A1/en
Publication of WO2023028825A1 publication Critical patent/WO2023028825A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Definitions

  • the present invention generally relates to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the same.
  • NAND storage devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products.
  • the planar NAND device is close to the limit of practical expansion.
  • 3D NAND memory is proposed.
  • a stacked memory structure is realized by vertically stacking multiple layers of data storage units.
  • the 3D NAND storage device also includes a control chip, and the control chip generally adopts Complementary Metal Oxide Semiconductor (COMS).
  • Complementary Metal Oxide Semiconductor In COMS, there will be both high voltage metal oxide semiconductor transistors (How Voltage Metal Oxide Semiconductor, HVMOS) and low voltage metal oxide semiconductor transistors (Low Voltage Metal Oxide Semiconductor, LVMOS). There may also be an ultra-low voltage metal oxide semiconductor transistor (Low Low Voltage Metal Oxide Semiconductor, LLVMOS) in CMOS, and the voltage of LLVMOS is lower than that of LVMOS.
  • HVMOS/LVMOS/LLVMOS devices such as shallow trench isolation (Shallow Trench Isolation, STI)
  • STI shallow trench isolation
  • the object of the present invention is to provide a semiconductor device and its preparation method, aiming at reducing the area of CMOS.
  • the present invention provides a method for preparing a semiconductor device, comprising:
  • second isolation tank
  • the depth of the first isolation groove in the longitudinal direction perpendicular to the substrate is greater than the depth of the second isolation groove in the longitudinal direction.
  • the widths of the first isolation groove and the second isolation groove in the transverse direction parallel to the substrate gradually decrease along the direction away from the surface of the substrate, and the second isolation groove The width of the top is greater than the width of the top of the first isolation groove.
  • the difference between the depths of the first isolation groove and the second isolation groove is equal to the depth of the first groove in the longitudinal direction.
  • the first trenches, the first isolation trenches and the second isolation trenches are respectively plural and arranged at intervals, and the plurality of the first trenches correspond to the plurality of the first isolation trenches one-to-one ; After the step of etching the substrate of the first device region, it also includes:
  • a first doped well region located between every two adjacent first trenches is formed in the substrate.
  • the step of forming a first doped well region between every two adjacent first trenches in the substrate includes:
  • the second sacrificial layer being located in the first device region and the second device region;
  • the second sacrificial layer located in the first device region is removed.
  • the step of etching the substrates of the first device region and the second device region includes:
  • the insulating layer is located above the first doped well region and on the inner surface of the first trench;
  • a hard mask layer is formed on the insulating layer and on the surface of the second sacrificial layer located in the second device region, and the hard mask layer has a plurality of grooves corresponding to a plurality of the first trenches one-to-one. a first opening and a plurality of second openings arranged at intervals corresponding to the second device area;
  • the insulating layer and the second sacrificial layer located in the second device region are etched by using the hard mask layer, so as to form a plurality of first doped well regions one-to-one corresponding to the plurality of first doped well regions.
  • the substrate is etched by using the hard mask layer to form a plurality of first isolation grooves corresponding to the plurality of first openings one by one, and forming a plurality of first isolation grooves corresponding to the plurality of first openings in the second device region. a plurality of second isolation slots corresponding to each second opening;
  • the hard mask layer is removed.
  • the step of etching the substrates of the first device region and the second device region further comprising:
  • a second doped well region located between every two adjacent second isolation trenches is formed in the substrate, and the depth of the second doped well region in the longitudinal direction is smaller than that of the first doped well region. The depth of the miscellaneous well region in the longitudinal direction.
  • Insulating material is filled in the first isolation groove and the second isolation groove.
  • the present invention provides a semiconductor device, comprising:
  • a substrate comprising a first device region and a second device region adjacent to the first device region;
  • At least one second isolation structure located in the substrate of the second device region; wherein, the depth of the first isolation structure in the longitudinal direction perpendicular to the substrate is greater than that of the second isolation structure in the longitudinal direction on the depth.
  • the widths of the first isolation structure and the second isolation structure in a lateral direction parallel to the substrate gradually decrease along a direction away from the surface of the substrate, and the second isolation structure
  • the top width of is greater than the top width of the first isolation structure.
  • the semiconductor device further includes:
  • the first isolation structure comprises: a first isolation trench and an insulating material filled in the first isolation trench;
  • the second isolation structure comprises a second isolation trench and an insulating material filled in the second isolation trench The insulating material in.
  • the present invention provides a semiconductor device and a manufacturing method thereof. Firstly, a substrate is provided, and the substrate includes a first device region and a second device region adjacent to the first device region, and then the first device region is The substrate of the first device region and the second device region are etched to form at least one first trench, and then the substrates of the first device region and the second device region are etched to form correspondingly at the position of the at least one first trench At least one first isolation trench and at least one second isolation trench are formed in the second device region. Wherein, the depth of the first isolation groove in the longitudinal direction perpendicular to the substrate is greater than the depth of the second isolation groove in the longitudinal direction.
  • the present invention can form the first isolation trench and the second isolation trench with different depths in the first device region and the second device region, so that the depths of the first isolation trench and the second isolation trench can meet the needs of the first device region and the second isolation trench at the same time.
  • the depth of the second isolation trench can also be reduced to reduce the area of the second device region, thereby reducing the area of the CMOS.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention
  • FIGS. 2a-2c are schematic structural diagrams during the manufacturing process of the semiconductor device provided by the first embodiment of the present invention.
  • Fig. 3 is a schematic flowchart of a method for preparing a first doped well region according to a second embodiment of the present invention
  • 4a-4e are structural schematic diagrams during the preparation process of the first doped well region provided by the second embodiment of the present invention.
  • Fig. 5 is a schematic flow chart of the preparation method of the first isolation groove and the second isolation groove provided by the second embodiment of the present invention
  • 6a-6e are structural schematic diagrams during the preparation process of the first isolation groove and the second isolation groove provided by the second embodiment of the present invention.
  • 6f-6h are structural schematic diagrams during the preparation process of the first isolation structure and the second isolation structure provided by the second embodiment of the present invention.
  • first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present invention.
  • the term "layer” refers to a portion of material that includes regions having a thickness.
  • the layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate.
  • a layer may extend across the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure.
  • a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure.
  • a layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. Layers may extend horizontally, vertically and/or along the tapered surface.
  • a substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. Layers may include multiple layers.
  • an interconnect layer may include one or more conductive layers and a contact layer (in which contacts, interconnect lines, and one or more dielectric layers are formed.
  • semiconductor device refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate; “vertical” means direction perpendicular to the substrate.
  • Fig. 1 is a schematic flow chart of the manufacturing method of the semiconductor device provided by the first embodiment of the present invention
  • Fig. 2a-2c is the preparation of the semiconductor device provided by the first embodiment of the present invention
  • Schematic diagram of the structure in the process, the manufacturing method of the semiconductor device includes the following steps S1-S5.
  • Step S1 providing a substrate 11 including a first device region 111 and a second device region 112 adjacent to the first device region 111 .
  • the substrate 11 may be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (Silicon On Insulator, SOI) or germanium on insulator (Germanium On Insulator, GOI), etc.
  • the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, and may also be a stacked structure, such as Si/SiGe and the like.
  • the device operating voltage corresponding to the first device region 111 is relatively high, and the device operating voltage corresponding to the second device region 112 is relatively low, so the device structures of the two are somewhat different, for example, the junction of the first device region 111 Deeper than the junction depth of the second device region 112, the thickness of the gate insulating layer of the first device region 111 is thicker than that of the second device region 112, and the gate of the first device region 111 is thicker than that of the second device region 112.
  • the grid is thicker etc.
  • Step S2 Etching the substrate 11 of the first device region 111 to form at least one first trench 113 .
  • the substrate 11 may be etched using a mask to form at least one first trench 113, and the depth of the first trench 113 is h0. Due to the influence of the etching process, the width of the first trench 113 in the lateral direction parallel to the substrate 11 gradually decreases along the direction away from the surface of the substrate 11 .
  • the "depth of the first groove 113" in this embodiment refers to the height from the upper surface of the substrate 11 to the bottom surface of the first groove 113, and other "depths" are based on the height of the substrate 11.
  • the upper surface of the base is the depth extending into the substrate 11 along the longitudinal direction. “Longitudinal” refers to a direction perpendicular to the substrate 11 .
  • step S3 in Fig. 1 and Fig. 2b Please refer to step S3 in Fig. 1 and Fig. 2b.
  • Step S3 forming a first doped well region 131 located between every two adjacent first trenches 113 in the substrate 11 .
  • a plurality of first doped well regions 131 can be formed by performing ion implantation on the substrate 11 between the first trenches 113 by using a mask.
  • step S4 Please refer to step S4 in Fig. 1 and Fig. 2b.
  • Step S4 Etching the substrate 11 of the first device region 111 and the second device region 112 to form at least one first isolation trench 114 at the position of the at least one first trench 113 and at the position of the at least one first trench 113 correspondingly. At least one second isolation trench 115 is formed in the second device region 112 .
  • This embodiment is described by taking the formation of multiple first isolation trenches 114 and multiple second isolation trenches 115 as an example. Specifically, continue to etch the substrate 11 of the first device region 111 and the second device region 112 to A first isolation trench 114 is formed corresponding to a trench 113 , and a plurality of second isolation trenches 115 are formed in the second device region 112 .
  • the substrate 11 of the first device region 111 has been etched for the first time in step S2
  • the substrates 11 of the first device region 111 and the second device region 112 have been etched for the second time in step S4 simultaneously and
  • the depth of etching is the same, and the two etching positions in the first device region 111 are the same (that is, the positions of the first isolation trench 114 and the first trench 113 are the same), so the depth h1 of the first isolation trench 114 formed finally It is deeper than the depth h2 of the second isolation trench 115, and the difference between the depth h1 of the first isolation trench 114 and the depth h2 of the second isolation trench 115 is equal to the depth h0 of the first trench 113 in FIG. 2a.
  • the depth h1 of the first isolation trench 114 may be equal to the depth of the first doped well region 131 .
  • the widths of the first isolation groove 114 and the second isolation groove 115 in the lateral direction parallel to the substrate 11 gradually decrease along the direction away from the surface of the substrate 11, that is, the first isolation groove 114 and the second isolation groove 115 are trapezoidal, so in order to ensure a constant width at the bottom, when the depth of the isolation groove is deeper, the opening required at the top is larger, so the occupied area is larger. Since the depth h2 of the second isolation trench 115 is smaller than the depth h1 of the first isolation trench 114, the top width W2 of the second isolation trench 115 is smaller than the top width W1 of the first isolation trench 114, thereby reducing the area of the second device region 112 .
  • Step S5 forming a second doped well region 132 between every two adjacent second isolation trenches 115 in the substrate 11, the second doped well region 132 in the longitudinal direction The depth is smaller than the depth of the first doped well region 131 in the vertical direction.
  • the second doped well region 132 can be formed by performing ion implantation on the substrate 11 between the second isolation trenches 115 using a mask. Since there are high-voltage devices in the first device region 111, a deeper junction depth is required, but for the low-voltage devices in the second device region 112, the required junction depth is shallower, so the junction depth of the second doped well region 132 It is shallower than the junction depth of the first doped well region 131 . It should be noted that “junction depth” refers to the vertical depth of the doped well region. Preferably, the depth of the second doped well region 132 may be equal to the depth h2 of the second isolation trench 115 .
  • the manufacturing method of the semiconductor device provided in this embodiment may further include: as shown in FIG. 2 c , filling the first isolation groove 114 and the second isolation groove 115 with an insulating material for better insulation.
  • the substrate 11 of the first device region 111 is etched to a certain depth h0 to form the first trench 113, and then the first device region 111 and the second device region 111 are simultaneously etched.
  • the substrate 11 in the region 112 is etched to form a first isolation trench 114 with a deeper depth at the position of the first trench 113, and to form a second isolation trench 115 in the second device region 112, so that the first isolation trench 114
  • the depth h1 is equal to the sum of the depth h0 of the first trench 113 and the depth h2 of the second isolation trench 115 .
  • the deeper first isolation trench 114 formed can be more The first doped well region 131 is well isolated.
  • the junction depth of the second doped well region 132 is relatively shallow, so forming the second isolation trench 115 shallower than the first isolation trench 114 can not only meet the requirement of isolating a plurality of second doped well regions 132, but also reduce the The depth of the second isolation trench 115 reduces the area of the second device region 112, thereby reducing the area of the entire semiconductor device.
  • Fig. 3 is a schematic flowchart of the method for preparing the first doped well region provided by the second embodiment of the present invention.
  • Figs. 4a-4e are provided by the second embodiment of the present invention Schematic diagram of the structure during the preparation process of the first doped well region.
  • the preparation method of the first doped well region includes the following steps S31-S36.
  • the structures in this embodiment that are the same as those in the first embodiment use the same symbols.
  • Step S31 forming a first sacrificial layer 121 on the substrate 11 .
  • the first sacrificial layer 121 may be formed after step S2 in the first embodiment (on the basis of FIG. 2a ), as shown in FIG. 4a, the first sacrificial layer 121 will be partially formed on the inner surface of the first groove 113,
  • the material of the first sacrificial layer 121 may include silicon oxide.
  • the first sacrificial layer 121 may also be formed before forming the first trench 113 (ie before FIG. 2 a ).
  • Step S32 performing the first ion implantation on the substrate 11 located between every two adjacent first trenches 113 .
  • the first device region 111 is a high-voltage device region, the energy of ion implantation in the first device region 111 is also very large, the first ion implantation forms the first initial doped well region 130, and the first sacrificial Layer 121 is used to protect substrate 11 from damage during the first ion implantation process.
  • Step S33 removing the first sacrificial layer 121 (as shown in FIG. 4c).
  • Hydrofluoric acid may be used for wet etching to remove the first sacrificial layer 121 .
  • Step S34 forming a second sacrificial layer 122 on the substrate 11, the second sacrificial layer 122 is located in the first device region 111 and the second device region 112 (as shown in FIG. 4d ).
  • the first sacrificial layer 121 is removed, and the second sacrificial layer 122 is re-deposited so as to protect the substrate 11 during the subsequent second ion implantation.
  • the material of the second sacrificial layer 122 may be silicon oxide.
  • Step S35 performing a second ion implantation on the substrate 11 located between each adjacent two of the plurality of first trenches 113 to form a second ion implantation located between each adjacent two of the plurality of first trenches 113
  • the first doped well region 131 The first doped well region 131 .
  • the difference between the second ion implantation and the first ion implantation is that the implanted ions are different, the implanted areas are different, or the implanted positions are different, and the three may also be different, so two ion implantations are required To form the first doped well region 131 to meet the requirements of the device.
  • Step S36 removing the second sacrificial layer 122 located in the first device region 111 (as shown in FIG. 4e ).
  • first doped well region 131 In the method for forming the first doped well region 131 in the second embodiment of the present invention, multiple first doped well regions 131 are formed by two ion implantations, and a sacrificial layer is formed on the substrate 11 before each ion implantation, The substrate 11 can be protected from damage, and the first doped well region 131 can meet the requirements of the device.
  • Fig. 5 is a schematic flow chart of the method for preparing the first isolation groove and the second isolation groove provided by the second embodiment of the present invention.
  • Fig. 6a-6e is the second embodiment of the present invention.
  • the example provides a schematic diagram of the structure during the preparation process of the first isolation groove and the second isolation groove.
  • the preparation method of the first isolation groove and the second isolation groove includes the following steps S41-S45.
  • Step S41 forming an insulating layer 14 on the substrate 11 of the first device region 111, the insulating layer 14 is located above the first doped well region 131 and on the inner surface of the first trench 113 .
  • a furnace tube oxidation process may be used to oxidize the surface of the substrate 10 to form an insulating layer 14, such as silicon dioxide.
  • Step S42 forming a hard mask layer 15 on the insulating layer 14 and on the surface of the second sacrificial layer 122 located in the second device region 112, the hard mask layer 15 has a A trench 113 corresponds to a plurality of first openings 153 one-to-one, and has a plurality of second openings 154 arranged at intervals corresponding to the second device region 112 .
  • the hard mask layer 15 may include a light absorbing layer 151 (such as silicon nitride) on the insulating layer 14 or the second sacrificial layer 122 and an antireflective layer 152 (such as nitrogen nitride) on the light absorbing layer 151 .
  • silicon oxide silicon oxide
  • silicon nitride, a silicon oxynitride layer, and photoresist may be sequentially formed first, and then a patterned photoresist layer is formed using a mask, and then the patterned photoresist layer is used to form the first opening 153 and the second opening 153. Two openings 154 in the hard mask layer 15 .
  • Step S43 using the hard mask layer 15 to etch the insulating layer 14 and the second sacrificial layer 122 located in the second device region 112 to form a plurality of first doped wells
  • the regions 131 correspond one-to-one to the plurality of first gate insulating layers 141 and the plurality of third sacrificial layers 123 located in the second device region 112 .
  • the material of the insulating layer 14 can be silicon dioxide, it can be used as a gate insulating layer. As shown in FIG. 6c, the insulating layer 14 located in the first trench 113 is removed based on the first opening 153 to form a plurality of first gate insulating layers 141, and at the same time, the second gate insulating layer located at the bottom of the second opening 154 is removed based on the second opening 154. sacrificial layer 122 to form a plurality of third sacrificial layers 123 , and the third sacrificial layer 123 can protect the substrate 10 during the process of forming the doped well region in the second device region 112 .
  • Step S44 using the hard mask layer 15 to etch the substrate 11 to form a plurality of first isolation grooves 114 corresponding to the plurality of first openings 153 one-to-one, and in the second A plurality of second isolation grooves 115 corresponding to the plurality of second openings 154 are formed in the device region 112 .
  • the widths of the first isolation groove 114 and the second isolation groove 115 in the lateral direction parallel to the substrate are respectively along the width away from the substrate 11.
  • the direction of the surface gradually decreases, that is, it gradually decreases from top to bottom. Since it is necessary to ensure that the bottom widths of the first isolation groove 114 and the second isolation groove 115 meet certain requirements, the deeper the depth, the greater the top width. Since the depth h2 of the second isolation trench 115 is smaller than the depth h1 of the first isolation trench 114 , the top width W2 of the second isolation trench 115 is smaller than the top width W1 of the first isolation trench 114 . It should be noted that the structural dimensions shown in the illustration do not represent the actual structural proportions.
  • the depth h2 of the second isolation trench 115 is as deep as the depth h1 of the first isolation trench 114 , so the top width W2 of the second isolation trench 115 is as wide as the top width W1 of the first isolation trench 114 .
  • the top width W2 of the second isolation trench 115 in this embodiment is reduced (less than the top width W1 of the first isolation trench), so the second isolation trench 115 prepared in this embodiment can reduce the size of the second device Area of District 112.
  • Step S45 removing the hard mask layer 15 (as shown in FIG. 6e).
  • Phosphoric acid may be used for wet etching to remove the hard mask layer 15 .
  • Figs. 6f-6h are structural schematic diagrams during the preparation process of the first isolation structure and the second isolation structure provided by the second embodiment of the present invention.
  • the manufacturing method of the semiconductor device may further include: 1) As shown in FIG.
  • the process for forming the second doped well region 132 may be the same as the process for forming the first doped well region 131 (refer to steps S31-S36). It can be understood that the third sacrificial layer 123 can protect the surface of the substrate 11 from damage when forming the second doped well region 132 for ion implantation. 2) As shown in FIG.
  • an insulating material 116 is filled in the first isolation trench 114 and the second isolation trench 115 to form the first isolation structure 16 and the second isolation structure 17.
  • remove The third sacrificial layer 123 forms a second gate insulating layer 142 on the surface of the substrate 11 of the second device region 112 .
  • the first gate insulating layer 141 is formed, thus saving process steps.
  • a substrate 11 is firstly provided, and the substrate 11 includes a first device region 111 and a second device region 112 adjacent to the first device region 111, and then The substrate 11 of the first device region 111 is etched to form a plurality of first trenches 113, and then the substrate 11 of the first device region 111 and the second device region 112 is etched to form a plurality of trenches 113 in the first device region 111 and the second device region 112.
  • the positions of the plurality of first trenches 113 correspond to the formation of a plurality of first isolation trenches 114 and the formation of a plurality of second isolation trenches 115 in the second device region 112 .
  • the depth h1 of the first isolation groove 114 in the longitudinal direction perpendicular to the substrate 11 is greater than the depth h2 of the second isolation groove 115 in the longitudinal direction, and the first isolation groove 114 and the second isolation groove 114 are The difference between the depths of the two isolation grooves 115 is equal to the depth h0 of the first groove 113 in the longitudinal direction.
  • the embodiment of the present invention can form the first isolation trench 114 and the second isolation trench 115 with different depths in the first device region 111 and the second device region 112, so that the depths of the first isolation trench 114 and the second isolation trench 115 can be simultaneously
  • An embodiment of the present invention also provides a semiconductor device, which can be formed according to the method for manufacturing a semiconductor device provided in the above embodiments, so refer to FIG. 6h.
  • the semiconductor device 10 includes: a substrate 11, the substrate 11 including a first device region 111 and a second device region 112 adjacent to the first device region 111; a substrate located in the first device region 111 at least one first isolation structure 16 in 11; at least one second isolation structure 17 in the substrate 11 of the second device region 112; wherein, the first isolation structure 16 is vertical to the substrate 11
  • the depth h1 in the longitudinal direction is greater than the depth h2 of the second isolation structure 17 in the longitudinal direction.
  • the widths of the first isolation structure 16 and the second isolation structure 17 in a lateral direction parallel to the substrate 11 gradually decrease along a direction away from the surface of the substrate 11, and
  • the top width W2 of the second isolation structure 17 is smaller than the top width W1 of the first isolation structure 16 .
  • the first isolation structure 16 includes: a first isolation trench 114 and an insulating material 116 filled in the first isolation trench 114; the second isolation structure 17 includes a second isolation trench 115 and The insulating material 116 filled in the second isolation trench 115 .
  • the first isolation structure 16 and the second isolation structure 17 are respectively multiple and arranged at intervals.
  • the semiconductor device 10 further includes: a first doped well region 131 located between every two adjacent first isolation structures 16 ; a second doped well region 131 located between every adjacent two of the second isolation structures 17 .
  • a doped well region 132, the depth of the second doped well region 132 in the longitudinal direction is smaller than the depth of the first doped well region 131 in the longitudinal direction.
  • the semiconductor device 10 may further include: a plurality of first gate insulating layers 141 located on the substrate 11 and corresponding to the plurality of first doped well regions 131; located on the substrate 11, And a plurality of second gate insulating layers 142 corresponding to the plurality of second doped well regions 132 one-to-one; wherein, the thickness of the first gate insulating layer 141 is greater than the thickness of the second gate insulating layer 142 .
  • the semiconductor device is formed by the manufacturing method of the semiconductor device provided in the above-mentioned embodiment, so it has the same beneficial effect as the above-mentioned embodiment, which will not be repeated in this embodiment.

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Abstract

本发明公开了一种半导体器件及其制备方法，先对第一器件区的衬底进行刻蚀形成至少一个第一沟槽，然后对第一器件区和第二器件区的衬底进行刻蚀，以在第一沟槽的位置对应形成第一隔离槽和在第二器件区形成第二隔离槽。其中，第一隔离槽的深度大于第二隔离槽的深度。

Description

一种半导体器件及其制备方法 技术领域
本发明总体上涉及电子器件，并且更具体的，涉及一种半导体器件及其制备方法。
背景技术
NAND存储器件是具有功耗低、质量轻且性能佳的非易失存储产品，在电子产品中得到了广泛的应用。平面结构的NAND器件已近实际扩展的极限，为了进一步的提高存储容量，降低每比特的存储成本，提出了3D NAND存储器。在3D NAND存储器结构中，采用垂直堆叠多层数据存储单元的方式，实现堆叠式的存储器结构。
3D NAND存储器件还包括控制芯片，控制芯片一般采用互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,COMS)。在COMS中会同时存在高压金属氧化物半导体晶体管(How Voltage Metal Oxide Semiconductor,HVMOS)和低压金属氧化物半导体晶体管(Low Voltage Metal Oxide Semiconductor,LVMOS)。CMOS中还可能存在超低压金属氧化物半导体晶体管(Low Low Voltage Metal Oxide Semiconductor,LLVMOS)，LLVMOS的电压比LVMOS的电压更低。
在目前的3D-NAND工艺中，我们现在一般都是把HVMOS/LVMOS/LLVMOS器件的隔离结构(如浅沟槽隔离(Shallow Trench Isolation,STI))做成了满足HVMOS的一样大的深度，这样LVMOS/LLVMOS其实是比需求做的更深了，这样就限制了LVMOS/LLVMOS的面积，导致LVMOS/LLVMOS器件的面积不能进一步缩小，也就限制了CMOS的面积。
技术问题
本发明的目的在于提供一种半导体器件及其制备方法，旨在缩小CMOS的面积。
技术解决方案
一方面，本发明提供一种半导体器件的制备方法，包括：
提供衬底，所述衬底包括第一器件区和与所述第一器件区相邻的第二器件区；
对所述第一器件区的衬底进行刻蚀，以形成至少一个第一沟槽；
对所述第一器件区和第二器件区的衬底进行刻蚀，以在所述至少一个第一沟槽的位置对应形成至少一个第一隔离槽和在所述第二器件区形成至少一个第二隔离槽；
其中，所述第一隔离槽在垂直于所述衬底的纵向上的深度大于所述第二隔离槽在所述纵向上的深度。
进一步优选的，所述第一隔离槽和第二隔离槽在平行于所述衬底的横向上的宽度，分别沿远离所述衬底的表面的方向逐渐减小，且所述第二隔离槽的顶部宽度大于所述第一隔离槽的顶部宽度。
进一步优选的，所述第一隔离槽与第二隔离槽的深度之差等于所述第一沟槽在所述纵向上的深度。
进一步优选的，所述第一沟槽、第一隔离槽和第二隔离槽分别为多个且各自间隔设置，且多个所述第一沟槽与多个所述第一隔离槽一一对应；所述对所述第一器件区的衬底进行刻蚀的步骤之后，还包括：
在所述衬底中形成位于每相邻两个所述第一沟槽之间的第一掺杂阱区。
进一步优选的，所述在所述衬底中形成位于每相邻两个所述第一沟槽之间的第一掺杂阱区的步骤，包括：
在所述衬底上形成第一牺牲层；
对位于每相邻两个所述第一沟槽之间的衬底进行第一次离子注入；
去除所述第一牺牲层；
在所述衬底上形成第二牺牲层，所述第二牺牲层位于所述第一器件区和第二器件区；
对位于每相邻两个所述多个第一沟槽之间的衬底进行第二次离子注入，以形成位于每相邻两个所述第一沟槽之间的第一掺杂阱区；
去除位于所述第一器件区的所述第二牺牲层。
进一步优选的，所述对所述第一器件区和第二器件区的衬底进行刻蚀的步 骤，包括：
在所述第一器件区的衬底上形成绝缘层，所述绝缘层位于所述第一掺杂阱区的上方和位于所述第一沟槽的内表面；
在所述绝缘层上和位于所述第二器件区的所述第二牺牲层的表面形成硬掩模层，所述硬掩模层具有与多个所述第一沟槽一一对应的多个第一开口、且具有对应所述第二器件区间隔设置的多个第二开口；
利用所述硬掩模层对所述绝缘层和位于所述第二器件区的所述第二牺牲层进行刻蚀，以形成与多个所述第一掺杂阱区一一对应的多个第一栅绝缘层和位于所述第二器件区的多个第三牺牲层；
利用所述硬掩模层对所述衬底进行刻蚀，以形成与所述多个第一开口一一对应的多个第一隔离槽，且在所述第二器件区形成与所述多个第二开口一一对应的多个第二隔离槽；
去除所述硬掩模层。
进一步优选的，所述对所述第一器件区和第二器件区的衬底进行刻蚀的步骤之后，还包括：
在所述衬底中形成位于每相邻两个所述第二隔离槽之间的第二掺杂阱区，所述第二掺杂阱区在所述纵向上的深度小于所述第一掺杂阱区在所述纵向上的深度。
进一步优选的，还包括：
在所述第一隔离槽和第二隔离槽中填充绝缘材料。
另一方面，本发明提供一种半导体器件，包括：
衬底，所述衬底包括第一器件区和与所述第一器件区相邻的第二器件区；
位于所述第一器件区的衬底中的至少一个第一隔离结构；
位于所述第二器件区的衬底中的至少一个第二隔离结构；其中，所述第一隔离结构在垂直于所述衬底的纵向上的深度大于所述第二隔离结构在所述纵向上的深度。
进一步优选的，所述第一隔离结构和第二隔离结构在平行于所述衬底的横向上的宽度，分别沿远离所述衬底的表面的方向逐渐减小，且所述第二隔离结构的顶部宽度大于所述第一隔离结构的顶部宽度。
进一步优选的，所述第一隔离结构和第二隔离结构分别为多个且各自间隔设置；所述半导体器件还包括：
位于每相邻两个所述第一隔离结构之间的第一掺杂阱区；
位于每相邻两个所述第二隔离结构之间的第二掺杂阱区，所述第二掺杂阱区在所述纵向上的深度小于所述第一掺杂阱区在所述纵向上的深度。
进一步优选的，所述第一隔离结构包括：第一隔离槽和填充在所述第一隔离槽中的绝缘材料；所述第二隔离结构包括第二隔离槽和填充在所述第二隔离槽中的所述绝缘材料。
有益效果
本发明提供一种半导体器件及其制备方法，先提供衬底，所述衬底包括第一器件区和与所述第一器件区相邻的第二器件区，再对所述第一器件区的衬底进行刻蚀，以形成至少一个第一沟槽，然后对所述第一器件区和第二器件区的衬底进行刻蚀，以在所述至少一个第一沟槽的位置对应形成至少一个第一隔离槽和在所述第二器件区形成至少一个第二隔离槽。其中，所述第一隔离槽在垂直于所述衬底的纵向上的深度大于所述第二隔离槽在所述纵向上的深度。本发明能够在第一器件区和第二器件区中形成不同深度的第一隔离槽和第二隔离槽，使第一隔离槽和第二隔离槽的深度能够同时满足第一器件区和第二器件区的要求，还能够减小第二隔离槽的深度从而缩小第二器件区的面积，进而缩小CMOS的面积。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1是本发明第一实施例提供的半导体器件的制备方法的流程示意图；
图2a-2c是本发明第一实施例提供的半导器件制备过程中的结构示意图；
图3是本发明第二实施例提供的第一掺杂阱区的制备方法的流程示意图；
图4a-4e是本发明第二实施例提供的第一掺杂阱区的制备过程中的结构示意图；
图5是本发明第二实施例提供的第一隔离槽和第二隔离槽的制备方法的 流程示意图；
图6a-6e是本发明第二实施例提供的第一隔离槽和第二隔离槽的制备过程中的结构示意图；
图6f-6h是本发明第二实施例提供的第一隔离结构和第二隔离结构的制备过程中的结构示意图。
本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
应当理解，虽然这里可使用术语第一、第二等描述各种组件，但这些组件不应受限于这些术语。这些术语用于使一个组件区别于另一个组件。例如，第一组件可以称为第二组件，类似地，第二组件可以称为第一组件，而不背离本发明的范围。
应当理解，当称一个组件在另一个组件“上”、“连接”另一个组件时，它可以直接在另一个组件上或者连接另一个组件，或者还可以存在插入的组件。其他的用于描述组件之间关系的词语应当以类似的方式解释。
如本文所使用的，术语“层”是指包括具有厚度的区域的材料部分。层具有顶侧和底侧，其中层的底侧相对靠近衬底，而顶侧相对远离衬底。层可以在整个下层或上层结构上延伸，或者可以具有小于下层或上层结构范围的范围。此外，层可以是厚度小于连续结构的厚度的均匀或不均匀连续结构的区域。例如，层可以位于连续结构的顶面和底面之间或在顶面和底面处的任何一组水平平面之间。层可以水平、垂直和/或沿着锥形表面延伸。衬底可以是层，其中可以包括一层或多层，和/或可以在其上、上方和/或其下具有一层或多层。层可以包括多个层。例如，互连层可以包括一个或多个导电层和触点层(其中形成有触点、互连线以及一个或多个电介质层。
如本文所使用的，术语“半导体器件”是指一种在横向定向的衬底上具有垂直定向的阵列结构的半导体器件，使得阵列结构相对于衬底在垂直方向上延伸； “垂直”是指垂直于衬底的方向。
需要说明的是，本发明实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更复杂。
请参阅图1，图1是本发明第一实施例提供的半导体器件的制备方法的流程示意图，请同时参阅图2a-2c，图2a-2c是本发明第一实施例提供的半导器件制备过程中的结构示意图，该半导体器件的制备方法包括以下步骤S1-S5。
请参见图1中的步骤S1-S2和图2a。
步骤S1：提供衬底11，所述衬底11包括第一器件区111和与所述第一器件区111相邻的第二器件区112。
衬底11可以为半导体衬底，例如可以为硅(Si)、锗(Ge)、SiGe衬底、绝缘体上硅(Silicon On Insulator，SOI)或绝缘体上锗(Germanium On Insulator，GOI)等。在其他实施例中，该半导体衬底还可以为包括其他元素半导体或者化合物半导体的衬底，还可以为叠层结构，例如Si/SiGe等。
在本实施例中，第一器件区111对应的器件工作电压较高，第二器件区112对应的器件工作电压较低，因此两者的器件结构会有些区别，比如第一器件区111的结深比第二器件区112的结深更深，第一器件区111的栅绝缘层厚度比第二器件区112的栅绝缘层更厚，第一器件区111的栅极比第二器件区112的栅极更厚等。
步骤S2：对所述第一器件区111的衬底11进行刻蚀，以形成至少一个第一沟槽113。
在本实施例中可以利用掩模板，对所述衬底11进行刻蚀工艺，以形成至少一个第一沟槽113，第一沟槽113的深度为h0。由于刻蚀工艺的影响，第一沟槽113在平行于衬底11的横向上的宽度沿远离衬底11表面的方向逐渐减小。需要说明的是，本实施例中的“第一沟槽113的深度”指的是从衬底11的上表面到第一沟槽113底表面的高度，其他“深度”都是以衬底11的上表面为基准沿纵向向衬底11内延伸的深度。“纵向”是指垂直于衬底11的方向。
请参见图1中的步骤S3和图2b。
步骤S3：在所述衬底11中形成位于每相邻两个所述第一沟槽113之间的第一掺杂阱区131。
在本实施例中，可以利用掩模板对第一沟槽113之间的衬底11进行离子注入形成多个第一掺杂阱区131。
请参见图1中的步骤S4和图2b。
步骤S4：对所述第一器件区111和第二器件区112的衬底11进行刻蚀，以在所述至少一个第一沟槽113的位置对应形成至少一个第一隔离槽114和在所述第二器件区112形成至少一个第二隔离槽115。
本实施例以形成多个第一隔离槽114和多个第二隔离槽115为例进行说明，具体的，继续刻蚀第一器件区111和第二器件区112的衬底11，以在第一沟槽113的位置对应形成第一隔离槽114，在第二器件区112形成多个第二隔离槽115。由于第一器件区111的衬底11在步骤S2中经过了第一次刻蚀，第一器件区111和第二器件区112的衬底11在步骤S4中同时经过了第二次刻蚀且刻蚀的深度相同，而在第一器件区111的两次刻蚀位置相同(即第一隔离槽114与第一沟槽113的位置相同)，所以最终形成的第一隔离槽114的深度h1比第二隔离槽115的深度h2更深，且第一隔离槽114的深度h1与第二隔离槽115的深度h2之差等于图2a中第一沟槽113的深度h0。优选的，第一隔离槽114的深度h1可以与第一掺杂阱区131的深度相等。
由于刻蚀工艺的影响，所述第一隔离槽114和第二隔离槽115在平行于衬底11的横向上的宽度，分别沿远离衬底11表面的方向逐渐减小，即第一隔离槽114和第二隔离槽115为梯形，因此为了保证底部宽度一定，当隔离槽深度越深时，其顶部需要的开口越大，因此占用的面积越大。由于第二隔离槽115的深度h2小于第一隔离槽114的深度h1，所以第二隔离槽115的顶部宽度W2小于第一隔离槽114的顶部宽度W1，从而可以缩小第二器件区112的面积。
请参见图1中的步骤S5和图2c。
步骤S5：在所述衬底11中形成位于每相邻两个所述第二隔离槽115之间的第二掺杂阱区132，所述第二掺杂阱区132在所述纵向上的深度小于所述第一掺杂阱区131在所述纵向上的深度。
在本实施例中，可以利用掩模板对第二隔离槽115之间的衬底11进行离子注入形成第二掺杂阱区132。由于第一器件区111中有高压器件，需要较深的结深，但是对于第二器件区112中的低压器件而言，需要的结深较浅，所以第二掺杂阱区132的结深比第一掺杂阱区131的结深更浅。需要说明的是，“结深”指的是掺杂阱区在纵向的深度。优选的，第二掺杂阱区132的深度可以与第二隔离槽115的深度h2相等。
本实施例提供的半导体器件的制备方法还可以包括：如图2c所示，在所述第一隔离槽114和第二隔离槽115中填充绝缘材料以起到更好的绝缘作用。
本发明第一实施例提供的半导体器件的制备方法，先将第一器件区111的衬底11刻蚀一定的深度h0形成第一沟槽113，再同时对第一器件区111和第二器件区112的衬底11进行刻蚀，以在第一沟槽113的位置形成深度更深的第一隔离槽114，以及在第二器件区112形成第二隔离槽115，因此第一隔离槽114的深度h1等于第一沟槽113的深度h0与第二隔离槽115的深度h2之和。由于第一掺杂阱区131的结深(即第一掺杂阱区131的深度)需要比第二掺杂阱区132的结深更深，因此形成的更深的第一隔离槽114可以对多个第一掺杂阱区131进行很好的隔离。而第二掺杂阱区132的结深较浅，因此形成比第一隔离槽114更浅的第二隔离槽115既能满足隔离多个第二掺杂阱区132的要求，又能减小第二隔离槽115的深度，从而减小第二器件区112的面积，进而缩小整个半导体器件的面积。
请参阅图3，图3是本发明第二实施例提供的第一掺杂阱区的制备方法的流程示意图，请同时参阅图4a-4e，图4a-4e是本发明第二实施例提供的第一掺杂阱区的制备过程中的结构示意图，该第一掺杂阱区的制备方法包括以下步骤S31-S36。为了便于理解，本实施例中与第一实施例相同的结构使用相同的标号。
步骤S31：在所述衬底11上形成第一牺牲层121。
可以在第一实施例中的步骤S2之后(图2a的基础上)形成第一牺牲层121，如图4a所示，第一牺牲层121会有部分形成在第一沟槽113的内表面，第一牺牲层121的材料可以包括氧化硅。在一些实施例中，第一牺牲层121也可以在形成第一沟槽113之前形成(即图2a之前)。
步骤S32：对位于每相邻两个所述第一沟槽113之间的衬底11进行第一次离子注入。
如图4b所示，由于第一器件区111是高压器件区，在第一器件区111进行离子注入的能量也非常大，第一次离子注入形成第一初始掺杂阱区130，第一牺牲层121用于保护第一次离子注入过程中衬底11不受损伤。
步骤S33：去除所述第一牺牲层121(如图4c所示)。
可以采用氢氟酸进行湿法刻蚀，以去除第一牺牲层121。
步骤S34：在所述衬底11上形成第二牺牲层122，所述第二牺牲层122位于所述第一器件区111和第二器件区112(如图4d所示)。
由于在步骤S32中的第一离子注入会使第一牺牲层121受到损伤，因此将第一牺牲层121去除，重新沉积第二牺牲层122以在后续进行第二次离子注入时对衬底11进行保护，第二牺牲层122的材料可以为氧化硅。
步骤S35：对位于每相邻两个所述多个第一沟槽113之间的衬底11进行第二次离子注入，以形成位于每相邻两个所述第一沟槽113之间的第一掺杂阱区131。
在本实施例中，第二次离子注入与第一离子注入的区别在于，注入的离子不同、注入的面积不同或注入的位置不同，也可能三者都不相同，因此需要进行两次离子注入来形成第一掺杂阱区131来满足器件的要求。
步骤S36：去除位于所述第一器件区111的所述第二牺牲层122(如图4e所示)。
本发明第二实施例中形成第一掺杂阱区131的方法，通过两次离子注入形成多个第一掺杂阱区131，且在每次离子注入之前在衬底11上形成牺牲层，可以保护衬底11不受损伤，且使第一掺杂阱区131能够满足器件的要求。
请参阅图5，图5是本发明第二实施例提供的第一隔离槽和第二隔离槽的制备方法的流程示意图，请同时参阅图6a-6e，图6a-6e是本发明第二实施例提供的第一隔离槽和第二隔离槽的制备过程中的结构示意图，该第一隔离槽和第二隔离槽的制备方法包括以下步骤S41-S45。
步骤S41：在所述第一器件区111的衬底11上形成绝缘层14，所述绝缘层14位于所述第一掺杂阱区131的上方和位于所述第一沟槽113的内表面。
如图6a所示，可以采用炉管氧化工艺，氧化衬底10的表面形成绝缘层14，例如二氧化硅。
步骤S42：在所述绝缘层14上和位于所述第二器件区112的所述第二牺牲层122的表面形成硬掩模层15，所述硬掩模层15具有与多个所述第一沟槽113一一对应的多个第一开口153、且具有对应所述第二器件区112间隔设置的多个第二开口154。
如图6b所示，硬掩模层15可以包括位于绝缘层14或第二牺牲层122上的吸光层151(如氮化硅)和位于所述吸光层151上的抗反射层152(如氮氧化硅)。具体的，可以先依次形成氮化硅、氮氧化硅层和光刻胶，再利用掩模板形成图案化光刻胶层，再利用所述图案化光刻胶层形成具有第一开口153和第二开口154的硬掩模层15。
步骤S43：利用所述硬掩模层15对所述绝缘层14和位于所述第二器件区112的所述第二牺牲层122进行刻蚀，以形成与多个所述第一掺杂阱区131一一对应的多个第一栅绝缘层141和位于所述第二器件区112的多个第三牺牲层123。
需要说明的是，由于绝缘层14的材料可以为二氧化硅，所以可以作为栅绝缘层。如图6c所示，基于第一开口153去除位于第一沟槽113中的绝缘层14以形成多个第一栅绝缘层141，同时基于第二开口154去除位于第二开口154底部的第二牺牲层122以形成多个第三牺牲层123，第三牺牲层123可以在第二器件区112中形成掺杂阱区的过程中保护衬底10。
步骤S44：利用所述硬掩模层15对所述衬底11进行刻蚀，以形成与所述多个第一开口153一一对应的多个第一隔离槽114，且在所述第二器件区112形成与所述多个第二开口154一一对应的多个第二隔离槽115。
如图6d所示，由于刻蚀工艺会造成一定的倾斜角度，因此第一隔离槽114和第二隔离槽115在平行于所述衬底的横向上的宽度，分别沿远离所述衬底11的表面的方向逐渐减小，即从上到下逐渐减小。由于需要保证第一隔离槽114和第二隔离槽115的底部宽度满足一定要求，因此深度越深，顶部宽度就越大。又由于第二隔离槽115的深度h2小于第一隔离槽114的深度h1，所以第二隔离槽115的顶部宽度W2小于第一隔离槽114的顶部宽度W1。需要说 明的是，图示结构尺寸不代表实际结构比例。
在现有技术中，第二隔离槽115的深度h2与第一隔离槽114的深度h1一样深，因此第二隔离槽115的顶部宽度W2与第一隔离槽114的顶部宽度W1一样宽。相比于现有技术，本实施例中第二隔离槽115的顶部宽度W2减小(小于第一隔离槽的顶部宽度W1)，因此本实施例制备的第二隔离槽115可以缩小第二器件区112的面积。
步骤S45：去除所述硬掩模层15(如图6e所示)。
可以采用磷酸进行湿法刻蚀，以去除硬掩模层15。
请参阅图6f-6h，图6f-6h是本发明第二实施例提供的第一隔离结构和第二隔离结构的制备过程中的结构示意图。在形成了第一隔离槽114和第二隔离槽115之后，该半导体器件的制备方法还可以包括：1)如图6f所示，在第二器件区112形成位于每相邻两个第二隔离槽115之间的第二掺杂阱区132，形成第二掺杂阱区132的工艺可以与形成第一掺杂阱区131的工艺相同(参照步骤S31-S36)。可以理解的是，第三牺牲层123可以在形成第二掺杂阱区132进行离子注入时保护衬底11表面不受损伤。2)如图6g所示，在所述第一隔离槽114和第二隔离槽115中填充绝缘材料116以形成第一隔离结构16和第二隔离结构17。3)如图6h所示，去除所述第三牺牲层123，在第二器件区112的衬底11表面形成第二栅绝缘层142。4)在第一栅绝缘层141和第二栅绝缘层142上形成栅极。
本发明第二实施例提供的第一隔离槽114和第二隔离槽115的制备方法中，形成了第一栅绝缘层141，因此节省了工艺步骤。
本发明实施例提供的半导体器件的制备方法，先提供衬底11，所述衬底11包括第一器件区111和与所述第一器件区111相邻的第二器件区112，再对所述第一器件区111的衬底11进行刻蚀，以形成多个第一沟槽113，然后对所述第一器件区111和第二器件区112的衬底11进行刻蚀，以在所述多个第一沟槽113的位置对应形成多个第一隔离槽114和在所述第二器件区112形成多个第二隔离槽115。其中，所述第一隔离槽114在垂直于所述衬底11的纵向上的深度h1大于所述第二隔离槽115在所述纵向上的深度h2，且所述第一隔离槽114与第二隔离槽115的深度之差等于所述第一沟槽113在所述纵向上的 深度h0。本发明实施例能够在第一器件区111和第二器件区112中形成不同深度的第一隔离槽114和第二隔离槽115，使第一隔离槽114和第二隔离槽115的深度能够同时满足第一器件区111和第二器件区112的要求，还能够减小第二隔离槽115的深度从而缩小第二器件区112的面积，进而缩小CMOS的面积。
本发明实施例还提供一种半导体器件，该半导体器件可以根据上述实施例提供的半导体器件的制备方法来形成，因此可以参照图6h。
该半导体器件10包括：衬底11，所述衬底11包括第一器件区111和与所述第一器件区111相邻的第二器件区112；位于所述第一器件区111的衬底11中的至少一个第一隔离结构16；位于所述第二器件区112的衬底11中的至少一个第二隔离结构17；其中，所述第一隔离结构16在垂直于所述衬底11的纵向上的深度h1大于所述第二隔离结构17在所述纵向上的深度h2。
在本实施例中，所述第一隔离结构16和第二隔离结构17在平行于所述衬底11的横向上的宽度，分别沿远离所述衬底11的表面的方向逐渐减小，且第二隔离结构17的顶部宽度W2小于第一隔离结构16的顶部宽度W1。
在本实施例中，所述第一隔离结构16包括：第一隔离槽114和填充在所述第一隔离槽114中的绝缘材料116；所述第二隔离结构17包括第二隔离槽115和填充在所述第二隔离槽115中的所述绝缘材料116。
可选的，所述第一隔离结构16和第二隔离结构17分别为多个且各自间隔设置。所述半导体器件10还包括：位于每相邻两个所述第一隔离结构16之间的第一掺杂阱区131；位于每相邻两个所述第二隔离结构17之间的第二掺杂阱区132，所述第二掺杂阱区132在所述纵向上的深度小于所述第一掺杂阱区131在所述纵向上的深度。
该半导体器件10还可以包括：位于所述衬底11上、且与多个所述第一掺杂阱区131一一对应的多个第一栅绝缘层141；位于所述衬底11上、且与多个所述第二掺杂阱区132一一对应的多个第二栅绝缘层142；其中，所述第一栅绝缘层141的厚度大于所述第二栅绝缘层142的厚度。
该半导体器件由上述实施例提供的半导体器件的制备方法来形成，因此具有与上述实施例相同的有益效果，在此实施例中不再赘述。
以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (12)

  1. 一种半导体器件的制备方法，其包括：
    提供衬底，所述衬底包括第一器件区和与所述第一器件区相邻的第二器件区；
    对所述第一器件区的衬底进行刻蚀，以形成至少一个第一沟槽；
    对所述第一器件区和第二器件区的衬底进行刻蚀，以在所述至少一个第一沟槽的位置对应形成至少一个第一隔离槽和在所述第二器件区形成至少一个第二隔离槽；
    其中，所述第一隔离槽在垂直于所述衬底的纵向上的深度大于所述第二隔离槽在所述纵向上的深度。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，所述第一隔离槽和第二隔离槽在平行于所述衬底的横向上的宽度，分别沿远离所述衬底的表面的方向逐渐减小，且所述第二隔离槽的顶部宽度大于所述第一隔离槽的顶部宽度。
  3. 根据权利要求1所述的半导体器件的制备方法，其中，所述第一隔离槽与第二隔离槽的深度之差等于所述第一沟槽在所述纵向上的深度。
  4. 根据权利要求1所述的半导体器件的制备方法，其中，所述第一沟槽、第一隔离槽和第二隔离槽分别为多个且各自间隔设置，且多个所述第一沟槽与多个所述第一隔离槽一一对应；所述对所述第一器件区的衬底进行刻蚀的步骤之后，还包括：
    在所述衬底中形成位于每相邻两个所述第一沟槽之间的第一掺杂阱区。
  5. 根据权利要求4所述的半导体器件的制备方法，其中，所述在所述衬底中形成位于每相邻两个所述第一沟槽之间的第一掺杂阱区的步骤，包括：
    在所述衬底上形成第一牺牲层；
    对位于每相邻两个所述第一沟槽之间的衬底进行第一次离子注入；
    去除所述第一牺牲层；
    在所述衬底上形成第二牺牲层，所述第二牺牲层位于所述第一器件区和第二器件区；
    对位于每相邻两个所述多个第一沟槽之间的衬底进行第二次离子注入，以 形成位于每相邻两个所述第一沟槽之间的第一掺杂阱区；
    去除位于所述第一器件区的所述第二牺牲层。
  6. 根据权利要求5所述的半导体器件的制备方法，其中，所述对所述第一器件区和第二器件区的衬底进行刻蚀的步骤，包括：
    在所述第一器件区的衬底上形成绝缘层，所述绝缘层位于所述第一掺杂阱区的上方和位于所述第一沟槽的内表面；
    在所述绝缘层上和位于所述第二器件区的所述第二牺牲层的表面形成硬掩模层，所述硬掩模层具有与多个所述第一沟槽一一对应的多个第一开口、且具有对应所述第二器件区间隔设置的多个第二开口；
    利用所述硬掩模层对所述绝缘层和位于所述第二器件区的所述第二牺牲层进行刻蚀，以形成与多个所述第一掺杂阱区一一对应的多个第一栅绝缘层和位于所述第二器件区的多个第三牺牲层；
    利用所述硬掩模层对所述衬底进行刻蚀，以形成与所述多个第一开口一一对应的多个第一隔离槽，且在所述第二器件区形成与所述多个第二开口一一对应的多个第二隔离槽；
    去除所述硬掩模层。
  7. 根据权利要求4所述的半导体器件的制备方法，其中，所述对所述第一器件区和第二器件区的衬底进行刻蚀的步骤之后，还包括：
    在所述衬底中形成位于每相邻两个所述第二隔离槽之间的第二掺杂阱区，所述第二掺杂阱区在所述纵向上的深度小于所述第一掺杂阱区在所述纵向上的深度。
  8. 根据权利要求1所述的半导体器件的制备方法，其中，还包括：
    在所述第一隔离槽和第二隔离槽中填充绝缘材料。
  9. 一种半导体器件，其包括：
    衬底，所述衬底包括第一器件区和与所述第一器件区相邻的第二器件区；
    位于所述第一器件区的衬底中的至少一个第一隔离结构；
    位于所述第二器件区的衬底中的至少一个第二隔离结构；
    其中，所述第一隔离结构在垂直于所述衬底的纵向上的深度大于所述第二隔离结构在所述纵向上的深度。
  10. 根据权利要求9所述的半导体器件，其中，所述第一隔离结构和第二隔离结构在平行于所述衬底的横向上的宽度，分别沿远离所述衬底的表面的方向逐渐减小，且所述第二隔离结构的顶部宽度大于所述第一隔离结构的顶部宽度。
  11. 根据权利要求9所述的半导体器件，其中，所述第一隔离结构和第二隔离结构分别为多个且各自间隔设置；所述半导体器件还包括：
    位于每相邻两个所述第一隔离结构之间的第一掺杂阱区；
    位于每相邻两个所述第二隔离结构之间的第二掺杂阱区，所述第二掺杂阱区在所述纵向上的深度小于所述第一掺杂阱区在所述纵向上的深度。
  12. 根据权利要求9所述的半导体器件，其中，所述第一隔离结构包括：第一隔离槽和填充在所述第一隔离槽中的绝缘材料；所述第二隔离结构包括第二隔离槽和填充在所述第二隔离槽中的所述绝缘材料。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101924025A (zh) * 2009-06-12 2010-12-22 中芯国际集成电路制造(上海)有限公司 浮栅制造方法
JP2012160544A (ja) * 2011-01-31 2012-08-23 Toyota Motor Corp 炭化珪素半導体装置の製造方法
CN102916024A (zh) * 2012-10-08 2013-02-06 上海华力微电子有限公司 一种形成双深度隔离沟槽的方法
CN113192890A (zh) * 2021-04-27 2021-07-30 长江存储科技有限责任公司 半导体器件的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101924025A (zh) * 2009-06-12 2010-12-22 中芯国际集成电路制造(上海)有限公司 浮栅制造方法
JP2012160544A (ja) * 2011-01-31 2012-08-23 Toyota Motor Corp 炭化珪素半導体装置の製造方法
CN102916024A (zh) * 2012-10-08 2013-02-06 上海华力微电子有限公司 一种形成双深度隔离沟槽的方法
CN113192890A (zh) * 2021-04-27 2021-07-30 长江存储科技有限责任公司 半导体器件的制造方法

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