KR100904569B1 - 비휘발성 반도체 메모리 및 그 제조 방법 - Google Patents

비휘발성 반도체 메모리 및 그 제조 방법 Download PDF

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KR100904569B1
KR100904569B1 KR1020070095295A KR20070095295A KR100904569B1 KR 100904569 B1 KR100904569 B1 KR 100904569B1 KR 1020070095295 A KR1020070095295 A KR 1020070095295A KR 20070095295 A KR20070095295 A KR 20070095295A KR 100904569 B1 KR100904569 B1 KR 100904569B1
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insulating film
gate electrode
gate insulating
layer
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KR20080026508A (ko
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도시따께 야에가시
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가부시끼가이샤 도시바
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Assigned to 도시바 메모리 가부시키가이샤 reassignment 도시바 메모리 가부시키가이샤 권리의 전부이전등록 Assignors: 가부시끼가이샤 도시바
Assigned to 키오시아 가부시키가이샤 reassignment 키오시아 가부시키가이샤 권리의 전부이전등록 Assignors: 도시바 메모리 가부시키가이샤
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020070095295A 2006-09-20 2007-09-19 비휘발성 반도체 메모리 및 그 제조 방법 Active KR100904569B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2006-00254710 2006-09-20
JP2006254710A JP4331189B2 (ja) 2006-09-20 2006-09-20 不揮発性半導体メモリ

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Publication Number Publication Date
KR20080026508A KR20080026508A (ko) 2008-03-25
KR100904569B1 true KR100904569B1 (ko) 2009-06-25

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US (3) US7928497B2 (https=)
JP (1) JP4331189B2 (https=)
KR (1) KR100904569B1 (https=)

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KR101375955B1 (ko) 2006-05-12 2014-03-18 애플 인크. 메모리 디바이스 내의 왜곡 추정 및 상쇄
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KR101509836B1 (ko) 2007-11-13 2015-04-06 애플 인크. 멀티 유닛 메모리 디바이스에서의 메모리 유닛의 최적화된 선택
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US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
JP5166095B2 (ja) 2008-03-31 2013-03-21 株式会社東芝 不揮発性半導体記憶装置の駆動方法及び不揮発性半導体記憶装置
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US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
JP5361328B2 (ja) 2008-10-27 2013-12-04 株式会社東芝 不揮発性半導体記憶装置の製造方法
US8713330B1 (en) 2008-10-30 2014-04-29 Apple Inc. Data scrambling in memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
KR20100095389A (ko) * 2009-02-20 2010-08-30 가부시끼가이샤 도시바 불휘발성 반도체 기억 장치 및 그 제조 방법
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US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
JP2011014838A (ja) * 2009-07-06 2011-01-20 Toshiba Corp 不揮発性半導体記憶装置
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
JP2011124321A (ja) * 2009-12-09 2011-06-23 Toshiba Corp 半導体装置の製造方法および半導体装置
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8677203B1 (en) 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
JP2011151072A (ja) * 2010-01-19 2011-08-04 Toshiba Corp 不揮発性半導体記憶装置
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
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JP5571010B2 (ja) 2011-01-28 2014-08-13 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5331141B2 (ja) * 2011-02-25 2013-10-30 株式会社東芝 不揮発性半導体記憶装置の製造方法
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US8994089B2 (en) * 2011-11-11 2015-03-31 Applied Materials, Inc. Interlayer polysilicon dielectric cap and method of forming thereof
CN103187439B (zh) * 2011-12-29 2015-08-05 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、cmos及其形成方法
KR102258369B1 (ko) 2014-06-23 2021-05-31 삼성전자주식회사 수직형 메모리 장치 및 이의 제조 방법
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US8211767B2 (en) 2012-07-03
US20080067576A1 (en) 2008-03-20
US20120238087A1 (en) 2012-09-20
US8723246B2 (en) 2014-05-13
JP4331189B2 (ja) 2009-09-16
US7928497B2 (en) 2011-04-19
KR20080026508A (ko) 2008-03-25
US20110165745A1 (en) 2011-07-07
JP2008078317A (ja) 2008-04-03

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