KR100855083B1 - 타겟 기판에 결합된 박막을 구비하는 적층 구조의 제조 방법 - Google Patents
타겟 기판에 결합된 박막을 구비하는 적층 구조의 제조 방법 Download PDFInfo
- Publication number
- KR100855083B1 KR100855083B1 KR1020037006179A KR20037006179A KR100855083B1 KR 100855083 B1 KR100855083 B1 KR 100855083B1 KR 1020037006179 A KR1020037006179 A KR 1020037006179A KR 20037006179 A KR20037006179 A KR 20037006179A KR 100855083 B1 KR100855083 B1 KR 100855083B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- contact
- thin layer
- contact surface
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR00/14170 | 2000-11-06 | ||
| FR0014170A FR2816445B1 (fr) | 2000-11-06 | 2000-11-06 | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
| PCT/FR2001/003401 WO2002037556A1 (fr) | 2000-11-06 | 2001-11-05 | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030051782A KR20030051782A (ko) | 2003-06-25 |
| KR100855083B1 true KR100855083B1 (ko) | 2008-08-29 |
Family
ID=8856075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020037006179A Expired - Lifetime KR100855083B1 (ko) | 2000-11-06 | 2001-11-05 | 타겟 기판에 결합된 박막을 구비하는 적층 구조의 제조 방법 |
Country Status (9)
| Country | Link |
|---|---|
| US (3) | US6974759B2 (enExample) |
| EP (1) | EP1344249B1 (enExample) |
| JP (3) | JP2004513517A (enExample) |
| KR (1) | KR100855083B1 (enExample) |
| CN (1) | CN1327505C (enExample) |
| AU (1) | AU2002223735A1 (enExample) |
| FR (1) | FR2816445B1 (enExample) |
| TW (1) | TW513752B (enExample) |
| WO (1) | WO2002037556A1 (enExample) |
Families Citing this family (306)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
| FR2894990B1 (fr) | 2005-12-21 | 2008-02-22 | Soitec Silicon On Insulator | Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede |
| FR2840731B3 (fr) * | 2002-06-11 | 2004-07-30 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
| US8507361B2 (en) | 2000-11-27 | 2013-08-13 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
| FR2840730B1 (fr) * | 2002-06-11 | 2005-05-27 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
| FR2835095B1 (fr) | 2002-01-22 | 2005-03-18 | Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique | |
| FR2835097B1 (fr) * | 2002-01-23 | 2005-10-14 | Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil | |
| FR2837981B1 (fr) * | 2002-03-28 | 2005-01-07 | Commissariat Energie Atomique | Procede de manipulation de couches semiconductrices pour leur amincissement |
| JP4277481B2 (ja) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | 半導体基板の製造方法、半導体装置の製造方法 |
| FR2842648B1 (fr) * | 2002-07-18 | 2005-01-14 | Commissariat Energie Atomique | Procede de transfert d'une couche mince electriquement active |
| FR2845523B1 (fr) | 2002-10-07 | 2005-10-28 | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee | |
| FR2845518B1 (fr) * | 2002-10-07 | 2005-10-14 | Commissariat Energie Atomique | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur |
| CN101800183B (zh) * | 2002-11-13 | 2013-02-06 | 日本冲信息株式会社 | 具有半导体薄膜的组合半导体装置 |
| JP4407127B2 (ja) * | 2003-01-10 | 2010-02-03 | 信越半導体株式会社 | Soiウエーハの製造方法 |
| TWI240434B (en) | 2003-06-24 | 2005-09-21 | Osram Opto Semiconductors Gmbh | Method to produce semiconductor-chips |
| FR2857953B1 (fr) * | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | Structure empilee, et procede pour la fabriquer |
| FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
| US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
| FR2858715B1 (fr) | 2003-08-04 | 2005-12-30 | Soitec Silicon On Insulator | Procede de detachement de couche de semiconducteur |
| US8475693B2 (en) | 2003-09-30 | 2013-07-02 | Soitec | Methods of making substrate structures having a weakened intermediate layer |
| FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
| FR2864336B1 (fr) | 2003-12-23 | 2006-04-28 | Commissariat Energie Atomique | Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci |
| US9011598B2 (en) | 2004-06-03 | 2015-04-21 | Soitec | Method for making a composite substrate and composite substrate according to the method |
| FR2872627B1 (fr) | 2004-06-30 | 2006-08-18 | Commissariat Energie Atomique | Assemblage par adhesion moleculaire de deux substrats |
| US7497907B2 (en) * | 2004-07-23 | 2009-03-03 | Memc Electronic Materials, Inc. | Partially devitrified crucible |
| EP1819508A1 (en) * | 2004-11-19 | 2007-08-22 | Akzo Nobel N.V. | Method for preparing flexible mechanically compensated transparent layered material |
| EP1681712A1 (en) * | 2005-01-13 | 2006-07-19 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Method of producing substrates for optoelectronic applications |
| TW200703462A (en) * | 2005-04-13 | 2007-01-16 | Univ California | Wafer separation technique for the fabrication of free-standing (Al, In, Ga)N wafers |
| FR2889887B1 (fr) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
| FR2895391B1 (fr) * | 2005-12-27 | 2008-01-25 | Commissariat Energie Atomique | Procede d'elaboration de nanostructures ordonnees |
| FR2895420B1 (fr) * | 2005-12-27 | 2008-02-22 | Tracit Technologies Sa | Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede. |
| FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
| FR2911598B1 (fr) * | 2007-01-22 | 2009-04-17 | Soitec Silicon On Insulator | Procede de rugosification de surface. |
| WO2008096194A1 (en) * | 2007-02-08 | 2008-08-14 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabrication of highly heat dissipative substrates |
| US7799656B2 (en) * | 2007-03-15 | 2010-09-21 | Dalsa Semiconductor Inc. | Microchannels for BioMEMS devices |
| US7776718B2 (en) * | 2007-06-25 | 2010-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor substrate with reduced gap size between single-crystalline layers |
| JP5498670B2 (ja) * | 2007-07-13 | 2014-05-21 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
| FR2920589B1 (fr) * | 2007-09-04 | 2010-12-03 | Soitec Silicon On Insulator | "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure" |
| JP5463017B2 (ja) * | 2007-09-21 | 2014-04-09 | 株式会社半導体エネルギー研究所 | 基板の作製方法 |
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| FR3116652A1 (fr) | 2020-11-26 | 2022-05-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procédé de fabrication d’un composant comprenant une couche en matériau monocristallin compatible avec des budgets thermiques élevés |
| US12237310B2 (en) | 2021-11-15 | 2025-02-25 | X-Celeprint Limited | Disaggregated transistor devices |
| FR3160054A1 (fr) | 2024-03-08 | 2025-09-12 | Soitec | Procede d’assemblage de deux substrats par adhesion moleculaire |
| FR3160049A1 (fr) | 2024-03-08 | 2025-09-12 | Soitec | Procede d’assemblage de deux substrats par adhesion moleculaire |
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- 2001-11-05 CN CNB018183360A patent/CN1327505C/zh not_active Expired - Lifetime
- 2001-11-05 KR KR1020037006179A patent/KR100855083B1/ko not_active Expired - Lifetime
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- 2001-11-05 JP JP2002540206A patent/JP2004513517A/ja active Pending
- 2001-11-05 WO PCT/FR2001/003401 patent/WO2002037556A1/fr not_active Ceased
- 2001-11-05 EP EP01993021.3A patent/EP1344249B1/fr not_active Expired - Lifetime
- 2001-11-05 AU AU2002223735A patent/AU2002223735A1/en not_active Abandoned
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| Publication number | Publication date |
|---|---|
| TW513752B (en) | 2002-12-11 |
| US8481409B2 (en) | 2013-07-09 |
| FR2816445A1 (fr) | 2002-05-10 |
| FR2816445B1 (fr) | 2003-07-25 |
| EP1344249A1 (fr) | 2003-09-17 |
| US20060079071A1 (en) | 2006-04-13 |
| EP1344249B1 (fr) | 2017-01-18 |
| CN1327505C (zh) | 2007-07-18 |
| JP5770767B2 (ja) | 2015-08-26 |
| JP2013138248A (ja) | 2013-07-11 |
| JP2004513517A (ja) | 2004-04-30 |
| US20040014299A1 (en) | 2004-01-22 |
| WO2002037556A1 (fr) | 2002-05-10 |
| US6974759B2 (en) | 2005-12-13 |
| CN1473361A (zh) | 2004-02-04 |
| JP2009081478A (ja) | 2009-04-16 |
| US20130230967A1 (en) | 2013-09-05 |
| AU2002223735A1 (en) | 2002-05-15 |
| US8679946B2 (en) | 2014-03-25 |
| KR20030051782A (ko) | 2003-06-25 |
| JP5528711B2 (ja) | 2014-06-25 |
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