KR100752885B1 - 반도체 칩 및 반도체 칩의 제조방법 - Google Patents

반도체 칩 및 반도체 칩의 제조방법 Download PDF

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KR100752885B1
KR100752885B1 KR1020000054904A KR20000054904A KR100752885B1 KR 100752885 B1 KR100752885 B1 KR 100752885B1 KR 1020000054904 A KR1020000054904 A KR 1020000054904A KR 20000054904 A KR20000054904 A KR 20000054904A KR 100752885 B1 KR100752885 B1 KR 100752885B1
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chip
wire
connection pad
bump
internal
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KR1020000054904A
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English (en)
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KR20010039901A (ko
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우에다시게유키
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로무 가부시키가이샤
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Abstract

본 발명은 다른 고체장치의 표면에 중첩시켜 접합되는 반도체 칩에 관한다.
이 반도체 칩은, 내부배선을 덮는 표면보호막과, 이 표면보호막으로부터 내부배선을 부분적으로 노출시키는 것에 의해 형성된 외부접속용 패드와, 이 외부접속용 패드 위에 내산화성을 갖는 금속재료를 사용하여 형성되며 외부단자와의 전기접속을 위한 와이어가 접속되는 와이어 접속부를 포함한다.
또한, 이 반도체 칩은, 다른 고체장치와의 접속을 위한 내부접속 패드와, 이 내부접속 패드 위에 형성된 범프를 포함하는 것이 바람직하다.

Description

반도체 칩 및 반도체 칩의 제조방법{SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME}
도 1은, 본 발명의 일실시형태에 관계하는 반도체 칩이 적용된 반도체장치의 개략구성을 나타내는 도해적인 단면도.
도 2는, 도 1에 나타내는 반도체장치에 구비되어 있는 주칩의 일부를 확대하여 나타낸 단면도.
(도면의 주요부분에 대한 부호의 설명)
1 : 주칩 2 : 부칩
3 : 패키지 4 : 본딩와이어
5 : 리드프레임 11 : 주칩의 표면
12 : 와이어 접속부 13 : 반도체기판
14 : 층간 절연막 15 : 내부배선
16 : 표면보호막 15A : 칩간 접속용 패드
15B : 외부접속용 패드 17A, 17B : 개구부
21 : 부칩의 표면 BM : 범프(주칩의)
BS : 범프(부칩의)
본 발명은, 반도체 칩 및 그 제조방법에 관한 것이다.
반도체 칩의 내부배선은, 비용절감을 위해, 알루미늄 등으로 구성되어 있는 것이 일반적이다.
이 알루미늄 등으로 이루어지는 배선은, 습기로 인한 산화를 받기 쉽다.
그 때문에, 배선의 표면은, 예를 들면 질화실리콘으로 이루어지는 표면보호막으로 덮여있다.
이 표면보호막에 개구부를 형성하여 배선의 일부를 노출시키는 것에 의해, 리드단자와 같은 외부단자와의 접속을 위한 외부접속용 패드가 형성되어 있다.
예를 들면 금(Au)으로 이루어지는 와이어의 한 끝을 외부접속용 패드에 부착시켜 접속하고, 와이어의 다른 끝을 외부단자에 접속시키는 것에 의하여, 반도체 칩의 배선과 외부단자와의 전기접속이 달성된다.
와이어가 외부접속용 패드에 접속된 이후는, 외부접속용 패드의 표면이 와이어로 모두 덮여지는 것이 바람직하다.
그런데, 예를 들면 외부접속용 패드 위에 있어서의 와이어의 부착면적이 적을 경우에는, 외부접속용 패드의 표면이 와이어로 다 덮이지 못하고, 외부접속용 패드의 일부가 노출된 채로 될 우려가 있다.
외부접속용 패드는, 알루미늄 등으로 구성되어 있기 때문에, 노출되어 있으 면 습기 등으로 산화되어 부식되어 버릴 우려가 있다.
본 발명의 목적은, 와이어의 접속상태에 관계없이, 외부접속용 패드가 부식될 우려 없는 반도체 칩 및 그 제조방법을 제공하는 것이다.
또, 본 발명의 다른 목적은, 상기와 같은 반도체 칩을 사용한 칩·온·칩 구조의 반도체장치 및 그 제조방법을 제공하는 것이다.
본 발명의 반도체 칩은, 내부배선을 덮는 표면보호막과, 이 표면보호막으로부터 상기 내부배선을 부분적으로 노출시키는 것에 의하여 형성된 외부접속용 패드와, 이 외부접속용 패드 위에 내산화성을 갖는 금속재료를 사용하여 형성되어 있으며, 외부단자와의 전기접속을 위한 와이어가 접속되는 와이어 접속부를 포함한다.
본 발명에 의하면, 외부접속용 패드 위에는, 내산화성을 갖는 금속재료로 이루어지는 와이어 접속부가 형성되어 있다.
바꾸어 말하면, 외부접속용 패드의 표면은, 내산화성을 갖는 금속재료로 이루어지는 와이어 접속부에 의하여 덮여있다.
이에 의해, 와이어 접속부에의 와이어의 접속상태에 관계없이, 외부접속용 패드가 외부에 노정되지 않기 때문에, 외부접속용 패드가 습기 등으로 산화되어 부식될 우려가 없다.
상기 반도체 칩은, 상기 표면보호막을 다른 고체장치(예를 들면, 다른 반도 체 칩)의 표면에 대향시킨 상태로, 그 다른 고체장치의 표면에 중첩시켜 접합되는 것으로 하여도 좋다.
이 경우에, 상기 반도체 칩은, 상기 외부접속용 패드와는 상이한 부분에서, 상기 표면보호막으로부터 상기 내부배선을 부분적으로 노출시키는 것에 의해 형성된 내부접속용 패드(칩 접속용 패드)와, 상기 다른 고체장치와의 전기접속을 위해, 내산화성을 갖는 금속재료를 사용하여 상기 내부접속용 패드(칩 접속용 패드)위에 융기(隆起)시켜 형성한 범프를 포함하는 것이 바람직하다.
또한, 이 경우, 상기 와이어 접속부는, 상기 범프와 동일한 재료로 구성되는 것이 바람직하다.
이렇게 함으로서, 와이어 접속부를 범프와 동일한 공정에서 형성할 수가 있다.
본 발명의 반도체 칩의 제조방법은, 다른 고체장치(예를 들면, 다른 반도체 칩)의 표면에 중첩시켜 접합되는 반도체 칩을 제조하는 방법으로서, 내부배선 위에 표면보호막을 적층시키는 공정과, 표면보호막에 개구를 형성하여 상기 내부배선을 부분적으로 노출시키는 것에 의하여 외부접속용 패드 및 내부접속용 패드(칩 접속용 패드)를 형성하는 공정과, 상기 외부접속용 패드 및 내부접속용 패드(칩 접속용 패드)위에 선택적으로 도금(바람직하게는, 내산화성 금속에 의한 도금)을 실시하여, 각각 외부단자와의 전기접속을 위한 와이어가 접속되는 와이어 접속부 및 다른 반도체 칩과의 전기접속을 위한 범프를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 칩의 제조방법이다.
이 방법에 의하면, 와이어 접속부를 범프와 동일한 공정에서 형성할 수가 있기 때문에, 외부접속용 패드 위에 와이어 접속부를 설치한 것에 의하여, 반도체 칩의 제조공정수가 증가하는 일은 없다.
또, 상기 와이어 접속부는, 상기 와이어와 동일한 재료로 구성되는 것이 바람직하다.
이렇게 함으로서, 와이어 접속부로의 와이어의 부착성을 향상시킬 수가 있다.
본 발명에 있어서 상기한, 또는 또다른 목적, 특징 및 효과는, 첨부도면을 참조하여 이하에 상술하는 실시형태의 설명으로 확실하게 될 것이다.
(실시예)
도 1은, 본 발명의 일실시형태에 관계하는 반도체 칩이 적용된 반도체장치의 개략구성을 나타내는 도해적인 단면도이다.
이 반도체 장치는, 소위 칩·온·칩 구조를 가지고 있으며, 주칩(1)의 표면(11)에 부칩(2)을 중첩시켜 접합시킨 후, 이들을 패키지(3)에 수납하는 것으로 구성되어 있다.
주칩(1) 및 부칩(2)은, 예를 들면 실리콘 칩으로 이루어진다.
주칩(1)의 표면(11)은, 주칩(1)의 기체를 이루는 반도체 기판에 있어서 트랜지스터 등의 기능소자가 형성된 활성표층 영역측의 표면이다.
표면(11)의 가장 표면은, 예를 들면 질화실리콘으로 구성되는 표면보호막(도시생략)으로 덮여있다.
이 표면보호막 위에는, 복수의 와이어 접속부(12)가 둘레테두리 부근에 배치되어 있다.
이 와이어 접속부(12)는, 예를 들면 금으로 이루어지는 본딩와이어(4)에 의하여 리드프레임(5)에 접속되어 있다.
또, 주칩(1)의 표면(11)에는, 부칩(2)과의 전기접속을 위한 복수개의 범프(BM)가 배치되어 있다.
부칩(2)은, 표면(21)을 주칩(1)의 표면(11)에 대향시킨, 이른바 페이스다운방식으로 주칩(1)에 접합되어 있다.
부칩(2)의 표면(21)은, 부칩(2)의 기체를 이루는 반도체 기판에 있어서 트랜지스터 등의 기능소자가 형성된 활성표층 영역측의 표면이다.
이 표면(21)의 가장 표면은, 예를 들면 질화실리콘으로 이루어지는 표면보호막(도시하지 않음)으로 덮여있다.
이 표면보호막 위에는, 내부배선에 접속된 복수개의 범프(BS)가 주칩(1)의 범프(BM)에 대향하여 배치되어 있다.
부칩(2)은, 범프(BS)가 각각 대향하는 주칩(1)의 범프(BM)에 접속된다.
이에 의하여, 부칩(2)은, 주칩(1)의 표면(11)과의 사이에 소정의 간격을 유지한 상태로 지지됨과 동시에, 주칩(1)과 전기적으로 접속되어 있다.
도 2는, 주칩(1)의 일부를 확대시켜 나타내는 단면도이다.
주칩(1)의 기체를 이루는 반도체기판(13)위에는, 예를 들면 산화실리콘으로 구성되는 층간 절연막(14)이 형성되어 있다.
이 층간 절연막(14)위에는, 예를 들면 알루미늄으로 이루어지는 내부배선(15)이 배설되어 있다.
층간 절연막(14) 및 내부배선(15)의 표면은, 예를 들면 질화실리콘으로 구성되는 표면보호막(16)으로 덮여있다.
그리고, 이 표면보호막(16)에 개구부(17A, 17B)를 형성하여, 표면보호막(16)으로부터 내부배선(15)을 부분적으로 노출시킴으로서, 각각 칩간 접속용 패드(15A) 및 외부접속용 패드(15B)가 형성되어 있다.
개구부(17A)내에 형성된 칩간 접속용 패드(15A)위에는, 내산화성 금속으로 이루어지는 범프(BM)가 융기하여 형성되어 있다.
한편, 외부접속용 패드(15B)는, 주칩(1)의 둘레 테두리부에 형성되어 있다.
이 외부접속용 패드(15B)위에는, 내산화성 금속을 사용하여, 본딩와이어(4)(도 1참조)를 접속시키기 위한 와이어 접속부(12)가 융기하여 형성되어 있다.
범프(BM) 및 와이어 접속부(12)를 구성하는 내산화성의 금속으로서는, 예를 들면, 금, 백금, 은, 팔라듐 또는 이리듐 등을 예시할 수가 있으며, 특히 금을 사용하는 것이 바람직하다.
또, 와이어 접속부(12)는, 본딩와이어(4)와 동일한 재료로 구성되는 것이 바람직하며, 이렇게 함으로서, 와이어 접속부(12)에로의 본딩와이어(4)의 부착성을 향상시킬 수가 있다.
또한, 범프(BM)와 와이어 접속부(12)는, 동일한 재료를 사용함으로서, 동일 공정에서 형성할 수가 있다.
예를 들면, 표면보호막(16)에 개구부(17A, 17B)를 형성한 후, 이 개구부(17A, 17B)가 형성된 표면보호막(16)위에 시드 막을 형성한다.
이 시드 막 위에, 칩간 접속용 패드(15A)[개구부(17A)] 및 외부접속용 패드(15B)[개구부(17B)]에 대응하는 개구를 갖는 레지스트 막을 패턴 형성한다.
그 후, 범프(BM) 및 와이어 접속부(12)의 재료를 사용한 도금을 실시한다.
그 후, 시드 막 위의 레지스트 막을 제거하고, 다시 레지스트 막의 제거에 의해 노출된 시드 막을 제거한다.
이에 의해, 칩간 접속용 패드(15A) 및 외부접속용 패드(15B)위에, 각각 범프(BM) 및 와이어 접속부(12)를 얻을 수가 있다.
이상과 같이 본 실시형태에 의하면, 외부접속용 패드(15B)[배선(15)]위에는, 내산화성을 갖는 금속재료로 이루어지는 와이어 접속부(12)가 융기하여 형성되어 있다.
바꾸어 말하면, 외부접속용 패드(15B)의 표면은, 내산화성을 갖는 금속재료로 이루어지는 와이어 접속부(12)에 의해 덮여있다.
그리고, 리드프레임(5)과의 전기접속을 위한 본딩와이어(4)는, 와이어 접속부(12)에 용착 되도록 되어 있다.
이에 의해, 와이어 접속부(12)에로의 본딩와이어(4)의 접속상태에 관계없이, 외부접속용 패드(15B)가 외부에 노정되는 일이 없기 때문에, 외부접속용 패드(15B)가 습기 등에 의해 산화 부식될 우려가 없다.
또, 와이어 접속부(12)는, 범프(BM)와 동일한 재료를 사용함으로서, 동일한 공정에서 형성될 수 있기 때문에, 이 와이어 접속부(12)를 설치하는 것에 의하여, 주칩(1)의 제조공정수가 증가하는 일은 없다.
단, 범프(BM)와 와이어 접속부(12)를 상이한 재료로 구성하여도 좋고, 이 경우에는, 와이어 접속부(12)는 범프(BM)와 별도의 공정에서 형성하게 된다.
이상, 본 발명의 한 실시형태에 대하여 설명하였으나, 본 발명은, 다른 형태에서도 실시할 수 있다.
예를 들면, 주칩(1) 및 부칩(2)은, 모두 실리콘으로 이루어지는 것으로 하였으나, 실리콘 이외에도, 화합물 반도체(예를 들면, 갈륨비소 반도체 등)나 게르마늄 반도체 등의 다른 임의의 반도체재료를 사용한 반도체 칩이라도 좋다.
이 경우에, 주칩(1)의 반도체재료와 부칩(2)의 반도체재료는, 동일하여도 좋고 상이하여도 좋다.
또, 상기의 실시형태에서는, 칩·온·칩 구조의 반도체장치를 채용하였으나, 본 발명에 있어서의 반도체 칩은, 칩·온·칩 구조 이외의 구조를 갖는 반도체장치에도 널리 적용시킬 수가 있다.
또한, 본 발명의 실시형태에 대하여 상세히 설명하였으나, 이들은 본 발명의 기술적 내용을 밝히기 위해 사용된 구체적인 예에 불과하며, 본 발명은 이들 구체예에 한정하여 해석될 수 없으며, 본 발명의 정신 및 범위는 첨부하는 청구범위에 의해서만 한정된다.
본 발명에 의하면, 외부접속용 패드 위에는, 내산화성을 갖는 금속재료로 이루어지는 와이어 접속부가 형성되어 있다.
바꾸어 말하면, 외부접속용 패드의 표면은, 내산화성을 갖는 금속재료로 이루어지는 와이어 접속부에 의하여 덮여있다.
이에 의해서, 와이어 접속부에의 와이어의 접속상태에 관계없이, 외부접속용 패드가 외부에 노정되지 않기 때문에, 외부접속용 패드가 습기 등으로 산화되어 부식될 우려가 없는 반도체 칩을 제공할 수 있다.

Claims (9)

  1. 내부배선을 덮는 표면보호막과,
    상기 표면보호막으로부터 상기 내부배선을 부분적으로 노출시키는 것에 의해 형성된 외부접속용 패드와,
    상기 외부접속용 패드 위에 내산화성을 갖는 금속재료를 사용하여 형성되며, 외부단자와의 전기접속을 위한 와이어가 접속되는 와이어 접속부와,
    상기 외부접속용 패드와는 상이한 부분에서, 상기 표면보호막으로부터 상기 내부배선을 부분적으로 노출시키는 것에 의해 형성된 내부접속용 패드와,
    다른 고체장치와의 전기접속을 위해, 내산화성을 갖는 금속재료를 사용하여 상기 내부접속용 패드 위에 융기하여 형성된 범프를 포함하고,
    상기 와이어 접속부는 상기 범프의 형상을 갖는 것을 특징으로 하는 반도체 칩.
  2. 제1항에 있어서,
    상기 반도체 칩은, 상기 표면보호막을 상기 다른 고체장치의 표면에 대향시킨 상태로, 상기 다른 고체장치의 표면에 중첩되어 접합되는 것을 특징으로 하는 반도체 칩.
  3. 삭제
  4. 제2항에 있어서,
    상기 다른 고체장치가 다른 반도체 칩인 것을 특징으로 하는 반도체 칩.
  5. 제1항 또는 제2항 또는 제4항 중 어느 한 항에 있어서,
    상기 와이어 접속부는 상기 범프와 동일한 재료로 구성되어 있는 것을 특징으로 하는 반도체 칩.
  6. 주칩의 표면에 부칩을 중첩시켜 접합한 칩·온·칩 구조의 반도체장치로서,
    상기 주칩은,
    내부배선을 덮는 표면보호막과,
    상기 표면보호막으로부터 상기 내부배선을 부분적으로 노출시키는 것에 의해 형성된 외부접속용 패드와,
    상기 외부접속용 패드 위에 내산화성을 갖는 금속재료를 사용하여 형성되며, 외부단자와의 전기접속을 위한 와이어가 접속되는 와이어 접속부와,
    상기 외부접속용 패드와는 상이한 부분에서, 상기 표면보호막으로부터 상기 내부배선을 부분적으로 노출시키는 것에 의해 형성된 내부접속용 패드와,
    내산화성을 갖는 금속재료를 사용하여 상기 내부접속용 패드 위에 융기하여 형성되며, 상기 주칩과 부칩을 전기접속시키는 범프를 포함하고,
    상기 와이어 접속부는 상기 범프의 형상을 갖는 것을 특징으로 하는 반도체장치.
  7. 제6항에 있어서,
    상기 와이어 접속부는 상기 범프와 동일한 재료로 구성되어 있는 것을 특징으로 하는 반도체장치.
  8. 다른 고체장치의 표면에 중첩시켜 접합되는 반도체 칩을 제조하는 방법으로서,
    내부배선 위에 표면보호막을 적층시키는 공정과,
    상기 표면보호막에 개구를 형성하여 상기 내부배선을 부분적으로 노출시키는 것에 의해 외부접속용 패드 및 내부접속용 패드를 형성하는 공정과,
    상기 외부접속용 패드 및 내부접속용 패드 위에 선택적으로 도금을 실시하는 것에 의해, 각각 외부단자와의 전기접속을 위한 와이어가 접속되는 와이어 접속부 및 다른 고체장치와의 전기접속을 위한 범프를 형성하는 공정을 포함하고,
    상기 와이어 접속부는 상기 범프의 형상을 갖는 것을 특징으로 하는 반도체 칩의 제조방법.
  9. 주칩의 표면에 부칩을 중첩시켜 접합한 칩·온·칩 구조의 반도체장치의 제조방법으로서,
    주칩의 내부배선 위에 표면보호막을 적층시키는 공정과,
    상기 표면보호막에 개구를 형성하여 상기 내부배선을 부분적으로 노출시키는 것에 의해 외부접속용 패드 및 내부접속용 패드를 형성하는 공정과,
    상기 외부접속용 패드 및 내부접속용 패드 위에 선택적으로 도금을 실시하는 것에 의해, 각각 외부단자와의 전기접속을 위한 와이어가 접속되는 와이어 접속부 및 상기 부칩과의 전기접속을 위한 범프를 형성하는 공정과,
    상기 범프를 통하여 주칩과 부칩을 접합시키는 공정을 포함하고,
    상기 와이어 접속부는 상기 범프의 형상을 갖는 특징으로 하는 반도체장치의 제조방법.
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