KR100629547B1 - Mram-장치 내에서의 바람직하지 않은 프로그래밍을예방하기 위한 방법 - Google Patents
Mram-장치 내에서의 바람직하지 않은 프로그래밍을예방하기 위한 방법 Download PDFInfo
- Publication number
- KR100629547B1 KR100629547B1 KR1020010067421A KR20010067421A KR100629547B1 KR 100629547 B1 KR100629547 B1 KR 100629547B1 KR 1020010067421 A KR1020010067421 A KR 1020010067421A KR 20010067421 A KR20010067421 A KR 20010067421A KR 100629547 B1 KR100629547 B1 KR 100629547B1
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- Prior art keywords
- memory cell
- magnetic field
- programming
- current
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (5)
- 삭제
- 메모리 셀 필드 내에서 메모리 셀(1: 11, 12, ...)이 적어도 하나의 평면에서 워드라인(WL) 또는 프로그래밍 라인(PRL)과 비트라인(BL)의 교차점에 놓이고, 선택된 메모리 셀(12)에 속하는 워드라인(WL1) 및 비트라인(BL2)을 통해 프로그래밍 전류(IWL; IBL2)가 보내지며, 상기 프로그래밍 전류는 선택된 상기 메모리 셀(12)에 인접한 적어도 하나의 메모리 셀(13)에서도 분산자계로서 작용하는 자계를 발생시키는 MRAM-장치 내에서의 바람직하지 않은 프로그래밍을 예방하기 위한 방법에 있어서,상기 인접한 메모리 셀(13)의 옆으로 연장되고 상기 선택된 메모리 셀(12)의 비트 라인(BL2)의 다음 다음 비트라인(BL4)을 통해 상기 분산자계와 반대 작용을 하는 보상자계를 제공하는 보상 전류가 전달되는 것을 특징으로 하는 방법.
- 제 2항에 있어서,상기 보상 전류는 프로그래밍 전류보다 더 약하게 설정되는 것을 특징으로 하는 방법.
- 제 2항 또는 제3항에 있어서,상기 보상 전류가 다층 시스템에서 다수의 평면에 있는 워드라인 또는 비트라인으로 인가되는 것을 특징으로 하는 방법.
- 제 2항 또는 제3항에 있어서,상기 보상 전류의 세기는 자기조절 회로에 의해 제어되는 것을 특징으로 하는 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10053965.3 | 2000-10-31 | ||
DE10053965A DE10053965A1 (de) | 2000-10-31 | 2000-10-31 | Verfahren zur Verhinderung unerwünschter Programmierungen in einer MRAM-Anordnung |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020042751A KR20020042751A (ko) | 2002-06-07 |
KR100629547B1 true KR100629547B1 (ko) | 2006-09-27 |
Family
ID=7661674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010067421A KR100629547B1 (ko) | 2000-10-31 | 2001-10-31 | Mram-장치 내에서의 바람직하지 않은 프로그래밍을예방하기 위한 방법 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6577527B2 (ko) |
EP (1) | EP1202284B1 (ko) |
JP (1) | JP3802794B2 (ko) |
KR (1) | KR100629547B1 (ko) |
CN (1) | CN1194353C (ko) |
DE (2) | DE10053965A1 (ko) |
TW (1) | TW527595B (ko) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270790A (ja) * | 2000-12-27 | 2002-09-20 | Toshiba Corp | 半導体記憶装置 |
JP3850702B2 (ja) * | 2001-09-18 | 2006-11-29 | 株式会社東芝 | 磁気抵抗メモリ装置及びその製造方法 |
JP4570313B2 (ja) | 2001-10-25 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
JP4074086B2 (ja) * | 2001-11-27 | 2008-04-09 | 株式会社東芝 | 磁気メモリ |
TW582032B (en) * | 2001-11-30 | 2004-04-01 | Toshiba Corp | Magnetic random access memory |
US6795334B2 (en) * | 2001-12-21 | 2004-09-21 | Kabushiki Kaisha Toshiba | Magnetic random access memory |
JP4033690B2 (ja) * | 2002-03-04 | 2008-01-16 | 株式会社ルネサステクノロジ | 半導体装置 |
US6778421B2 (en) * | 2002-03-14 | 2004-08-17 | Hewlett-Packard Development Company, Lp. | Memory device array having a pair of magnetic bits sharing a common conductor line |
US20030218905A1 (en) * | 2002-05-22 | 2003-11-27 | Perner Frederick A. | Equi-potential sensing magnetic random access memory (MRAM) with series diodes |
JP4208500B2 (ja) * | 2002-06-27 | 2009-01-14 | 株式会社ルネサステクノロジ | 薄膜磁性体記憶装置 |
JP2004241013A (ja) * | 2003-02-03 | 2004-08-26 | Renesas Technology Corp | 半導体記憶装置 |
JP2004259353A (ja) | 2003-02-25 | 2004-09-16 | Sony Corp | 不揮発性磁気メモリ装置、及び、不揮発性磁気メモリ装置におけるトンネル磁気抵抗素子へのデータ書込方法 |
JP4290494B2 (ja) * | 2003-07-08 | 2009-07-08 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
US6906941B2 (en) * | 2003-07-22 | 2005-06-14 | Hewlett-Packard Development Company, L.P. | Magnetic memory structure |
US7474547B2 (en) * | 2003-09-02 | 2009-01-06 | Nxp B.V. | Active shielding for a circuit comprising magnetically sensitive materials |
US6859388B1 (en) | 2003-09-05 | 2005-02-22 | Freescale Semiconductor, Inc. | Circuit for write field disturbance cancellation in an MRAM and method of operation |
KR100835275B1 (ko) | 2004-08-12 | 2008-06-05 | 삼성전자주식회사 | 스핀 주입 메카니즘을 사용하여 자기램 소자를 구동시키는방법들 |
KR20060111521A (ko) * | 2003-11-24 | 2006-10-27 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 자기저항 메모리장치를 프로그래밍하는 동안에 액티브 필드보상을 수행하기 위한 방법 및 장치 |
US7397074B2 (en) * | 2005-01-12 | 2008-07-08 | Samsung Electronics Co., Ltd. | RF field heated diodes for providing thermally assisted switching to magnetic memory elements |
US7362644B2 (en) * | 2005-12-20 | 2008-04-22 | Magic Technologies, Inc. | Configurable MRAM and method of configuration |
KR100817061B1 (ko) * | 2006-09-26 | 2008-03-27 | 삼성전자주식회사 | 기입 전류와 같은 방향의 금지 전류를 흐르게 하는마그네틱 램 |
US8437181B2 (en) | 2010-06-29 | 2013-05-07 | Magic Technologies, Inc. | Shared bit line SMT MRAM array with shunting transistors between the bit lines |
KR20140021781A (ko) | 2012-08-10 | 2014-02-20 | 삼성전자주식회사 | 가변 저항 메모리를 포함하는 반도체 메모리 장치 |
KR101266792B1 (ko) * | 2012-09-21 | 2013-05-27 | 고려대학교 산학협력단 | 면내 전류와 전기장을 이용한 수평형 자기메모리 소자 |
US9666257B2 (en) | 2015-04-24 | 2017-05-30 | Intel Corporation | Bitcell state retention |
US11031059B2 (en) * | 2019-02-21 | 2021-06-08 | Sandisk Technologies Llc | Magnetic random-access memory with selector voltage compensation |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6097626A (en) * | 1999-07-28 | 2000-08-01 | Hewlett-Packard Company | MRAM device using magnetic field bias to suppress inadvertent switching of half-selected memory cells |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US3456247A (en) * | 1966-01-14 | 1969-07-15 | Ibm | Coupled film storage device |
US3593325A (en) * | 1969-01-15 | 1971-07-13 | Inst Elektronik Dresden | Magnetic thin film storage device for nondestructive readout thereof |
US5039655A (en) * | 1989-07-28 | 1991-08-13 | Ampex Corporation | Thin film memory device having superconductor keeper for eliminating magnetic domain creep |
TW411471B (en) * | 1997-09-17 | 2000-11-11 | Siemens Ag | Memory-cell device |
US6404671B1 (en) * | 2001-08-21 | 2002-06-11 | International Business Machines Corporation | Data-dependent field compensation for writing magnetic random access memories |
-
2000
- 2000-10-31 DE DE10053965A patent/DE10053965A1/de not_active Ceased
-
2001
- 2001-09-11 EP EP01121863A patent/EP1202284B1/de not_active Expired - Lifetime
- 2001-09-11 DE DE50109266T patent/DE50109266D1/de not_active Expired - Fee Related
- 2001-10-29 JP JP2001331484A patent/JP3802794B2/ja not_active Expired - Fee Related
- 2001-10-30 TW TW090126915A patent/TW527595B/zh not_active IP Right Cessation
- 2001-10-31 US US09/999,324 patent/US6577527B2/en not_active Expired - Fee Related
- 2001-10-31 CN CNB01137795XA patent/CN1194353C/zh not_active Expired - Fee Related
- 2001-10-31 KR KR1020010067421A patent/KR100629547B1/ko not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6097626A (en) * | 1999-07-28 | 2000-08-01 | Hewlett-Packard Company | MRAM device using magnetic field bias to suppress inadvertent switching of half-selected memory cells |
Also Published As
Publication number | Publication date |
---|---|
EP1202284A2 (de) | 2002-05-02 |
CN1194353C (zh) | 2005-03-23 |
TW527595B (en) | 2003-04-11 |
US6577527B2 (en) | 2003-06-10 |
EP1202284B1 (de) | 2006-03-22 |
US20020085411A1 (en) | 2002-07-04 |
JP3802794B2 (ja) | 2006-07-26 |
DE10053965A1 (de) | 2002-06-20 |
DE50109266D1 (de) | 2006-05-11 |
EP1202284A3 (de) | 2004-01-02 |
KR20020042751A (ko) | 2002-06-07 |
JP2002203388A (ja) | 2002-07-19 |
CN1355535A (zh) | 2002-06-26 |
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