KR100503940B1 - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR100503940B1
KR100503940B1 KR10-2003-0005706A KR20030005706A KR100503940B1 KR 100503940 B1 KR100503940 B1 KR 100503940B1 KR 20030005706 A KR20030005706 A KR 20030005706A KR 100503940 B1 KR100503940 B1 KR 100503940B1
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South Korea
Prior art keywords
film
plating
electrode
insulating film
organic insulating
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Expired - Fee Related
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KR10-2003-0005706A
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English (en)
Korean (ko)
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KR20030090489A (ko
Inventor
네모토요시히코
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미쓰비시덴키 가부시키가이샤
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Publication of KR100503940B1 publication Critical patent/KR100503940B1/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
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    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/13005Structure
    • H01L2224/13007Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemically Coating (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR10-2003-0005706A 2002-05-20 2003-01-29 반도체장치 및 그 제조방법 Expired - Fee Related KR100503940B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002145333A JP2003338516A (ja) 2002-05-20 2002-05-20 半導体装置およびその製造方法
JPJP-P-2002-00145333 2002-05-20

Publications (2)

Publication Number Publication Date
KR20030090489A KR20030090489A (ko) 2003-11-28
KR100503940B1 true KR100503940B1 (ko) 2005-07-26

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KR10-2003-0005706A Expired - Fee Related KR100503940B1 (ko) 2002-05-20 2003-01-29 반도체장치 및 그 제조방법

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Country Link
US (1) US6686660B2 (enExample)
JP (1) JP2003338516A (enExample)
KR (1) KR100503940B1 (enExample)
DE (1) DE10261460A1 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005265720A (ja) * 2004-03-19 2005-09-29 Nec Corp 電気接点構造及びその形成方法と素子検査方法
CN100468674C (zh) * 2004-11-25 2009-03-11 日本电气株式会社 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置
KR20080037681A (ko) * 2005-08-23 2008-04-30 로무 가부시키가이샤 반도체 칩 및 그 제조 방법 및 반도체 장치
JP2007184381A (ja) * 2006-01-06 2007-07-19 Matsushita Electric Ind Co Ltd フリップチップ実装用回路基板とその製造方法、並びに半導体装置とその製造方法
JP2007243031A (ja) * 2006-03-10 2007-09-20 Seiko Epson Corp 配線基板の製造方法
KR100771675B1 (ko) * 2006-03-30 2007-11-01 엘지전자 주식회사 패키지용 인쇄회로기판 및 그 제조방법
US7538429B2 (en) * 2006-08-21 2009-05-26 Intel Corporation Method of enabling solder deposition on a substrate and electronic package formed thereby
US20080136019A1 (en) * 2006-12-11 2008-06-12 Johnson Michael E Solder Bump/Under Bump Metallurgy Structure for High Temperature Applications
US8555494B2 (en) * 2007-10-01 2013-10-15 Intel Corporation Method of manufacturing coreless substrate
US8058726B1 (en) * 2008-05-07 2011-11-15 Amkor Technology, Inc. Semiconductor device having redistribution layer
US9543262B1 (en) 2009-08-18 2017-01-10 Cypress Semiconductor Corporation Self aligned bump passivation
US8455361B2 (en) * 2010-01-07 2013-06-04 Texas Instruments Incorporated Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device
US8362612B1 (en) 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8552557B1 (en) 2011-12-15 2013-10-08 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8664090B1 (en) 2012-04-16 2014-03-04 Amkor Technology, Inc. Electronic component package fabrication method
US9245862B1 (en) 2013-02-12 2016-01-26 Amkor Technology, Inc. Electronic component package fabrication method and structure
WO2015107796A1 (ja) * 2014-01-20 2015-07-23 三菱電機株式会社 半導体素子およびその製造方法、ならびに半導体装置
JP6406975B2 (ja) * 2014-10-24 2018-10-17 三菱電機株式会社 半導体素子および半導体装置
JP2017069381A (ja) 2015-09-30 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP2018137290A (ja) * 2017-02-20 2018-08-30 トヨタ自動車株式会社 半導体装置
JP7235541B2 (ja) 2019-03-11 2023-03-08 株式会社東芝 半導体装置およびその製造方法
KR20230076151A (ko) * 2021-11-22 2023-05-31 삼성전자주식회사 반도체 패키지

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02276249A (ja) 1989-04-18 1990-11-13 Seiko Epson Corp 半導体回路バンプの製造方法
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
JPH1140745A (ja) 1997-07-17 1999-02-12 Hitachi Ltd 半導体装置およびその半導体装置を組み込んだ電子装置
JPH11214421A (ja) 1997-10-13 1999-08-06 Matsushita Electric Ind Co Ltd 半導体素子の電極形成方法

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JP2003338516A (ja) 2003-11-28
US6686660B2 (en) 2004-02-03
DE10261460A1 (de) 2003-12-11
US20030214038A1 (en) 2003-11-20
KR20030090489A (ko) 2003-11-28

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