JP7235541B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

Info

Publication number
JP7235541B2
JP7235541B2 JP2019044019A JP2019044019A JP7235541B2 JP 7235541 B2 JP7235541 B2 JP 7235541B2 JP 2019044019 A JP2019044019 A JP 2019044019A JP 2019044019 A JP2019044019 A JP 2019044019A JP 7235541 B2 JP7235541 B2 JP 7235541B2
Authority
JP
Japan
Prior art keywords
metal layer
electrode
outer edge
insulating layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019044019A
Other languages
English (en)
Other versions
JP2020150030A (ja
Inventor
智洋 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Priority to JP2019044019A priority Critical patent/JP7235541B2/ja
Priority to CN201910676240.6A priority patent/CN111682005B/zh
Priority to US16/540,159 priority patent/US10998257B2/en
Publication of JP2020150030A publication Critical patent/JP2020150030A/ja
Application granted granted Critical
Publication of JP7235541B2 publication Critical patent/JP7235541B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04034—Bonding areas specifically adapted for strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3001—Structure
    • H01L2224/3003—Layer connectors having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3005—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/84399—Material
    • H01L2224/844—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

実施形態は、半導体装置およびその製造方法に関する。
大電力の制御に用いられる半導体装置は、コネクタまたはバスバーなどの板状の接続導体を用いて電源回路に接続される。このため、半導体上の電極と接続導体との間に接合部材を配置する必要がある。
特開２００３－３３８５１６号公報
実施形態は、半導体上の電極と接続導体との間に設けられる接続構造の信頼性を向上させた半導体装置およびその製造方法を提供する。
実施形態に係る半導体装置は、半導体部と、前記半導体部上に設けられ、前記半導体部に電気的に接続された電極と、前記電極の表面上に選択的に設けられた第１金属層と、前記電極上において前記第１金属層を囲み、前記第１金属層の外縁の上面に接する第１表面を有する絶縁層と、前記第１金属層上に設けられた第２金属層と、前記第１金属層および前記第２金属層の間に設けられた第３金属層と、を備える。前記第２金属層は、前記絶縁層の前記第１表面に連続する前記絶縁層の第２表面に接する外縁を有する。前記第３金属層の外縁および前記第３金属層の前記外縁の上面は、前記絶縁層の前記第１表面と前記第２表面との間に位置する第３表面に接する。
実施形態に係る半導体装置を示す模式断面図である。 実施形態に係る半導体素子の電極構造を示す模式断面図である。 実施形態に係る半導体素子の製造過程を示す模式断面図である。 図３に続く製造過程を示す模式断面図である。 比較例に係る半導体素子の電極構造を示す模式断面図である。 実施形態の第１変形例に係る半導体素子の電極構造を示す模式断面図である。 実施形態の第１変形例に係る半導体素子の製造過程を示す模式断面図である。 実施形態の第２変形例に係る半導体素子の電極構造を示す模式断面図である。 実施形態の第３変形例に係る半導体素子の電極構造を示す模式断面図である。 実施形態の第３変形例に係る半導体素子の製造過程を示す模式断面図である。
以下、実施の形態について図面を参照しながら説明する。図面中の同一部分には、同一番号を付してその詳しい説明は適宜省略し、異なる部分について説明する。なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
さらに、各図中に示すＸ軸、Ｙ軸およびＺ軸を用いて各部分の配置および構成を説明する。Ｘ軸、Ｙ軸、Ｚ軸は、相互に直交し、それぞれＸ方向、Ｙ方向、Ｚ方向を表す。また、Ｚ方向を上方、その反対方向を下方として説明する場合がある。
図１は、実施形態に係る半導体装置１００を示す模式断面図である。半導体装置１００は、例えば、半導体素子１と、実装基板１０と、接続導体２０と、を備える。
図１に示すように、実装基板１０は、マウントパッド１１と、配線１３と、を含む。マウントパッド１１は、実装基板１０の表面上に設けられる。半導体素子１は、マウントパッド１１の上に接続部材１５を介してマウントされる。半導体素子１は、接続導体２０を介して配線１３に電気的に接続される。
半導体素子１は、半導体部３０と、電極３１と、電極３３と、金属層３５と、絶縁層３７と、金属層３９と、を含む。半導体素子１は、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transisitor）である。電極３１は、例えば、コレクタ電極であり、電極３３は、例えば、エミッタ電極である。半導体部３０は、例えば、シリコンである。
電極３１は、半導体部３０の裏面上に設けられる。電極３３は、半導体部３０の表面上に設けられる。金属層３５は、電極３３の上に選択的に設けられる。絶縁層３７は、電極３３上において金属層３５を囲むように設けられる。金属層３９は、金属層３５の上に設けられる。
接続導体２０は、例えば、銅板であり、接続部材２３を介して金属層３９上にボンディングされる。また、接続導体２０は、接続部材２５を介して配線１３上にボンディングされる。接続部材２３および２５は、例えば、ハンダ材である。
半導体装置１００は、上記の例に限定される訳ではない。例えば、半導体素子１は、ＭＯＳＦＥＴもしくはダイオードであっても良い。また、実装基板１０は、例えば、銅フレームに置き換えても良い。
図２は、実施形態に係る半導体素子１の電極構造を示す模式断面図である。半導体素子１は、例えば、電極３３の上に積層された金属層３５、金属層３８および金属層３９とを含む。電極３３は、例えば、アルミニウム電極である。また、電極３３の材料は、銅を含む金属であっても良い。金属層３５は、例えば、ニッケル層である。金属層３８は、例えば、パラジウム層である。金属層３９は、例えば、金（Ａｕ）層である。
金属層３９は、接続部材２３を介した接続導体２０のボンディング強度を向上させるために用いられる。例えば、接続部材２３と金属層３９との間の密着強度（図１参照）は、接続部材２３を金属層３５に直接接するように配置した場合の接続部材２３の密着強度よりも大きい。金属層３８は、例えば、実装時の熱により金属層３５の金属原子が金属層３９の中に拡散し、接続部材２３と金属層３９との間の密着強度が低下することを防ぐために設けられる。すなわち、金属層３８は、所謂バリア層である。なお、金属層３９を、例えば、０．１μｍ以上の厚さ形成する場合には、金属層３８は省略可能である。
図２に示すように、金属層３５は、その外縁３５ｅが絶縁層３７の内面に沿うように設けられる。また、金属層３８の外縁３８ｅおよび金属層３９の外縁３９ｅも絶縁層３７に沿うように設けられる。
例えば、電極３３の表面に垂直な方向（Ｚ方向）において、絶縁層３７の厚さは、金属層３５、金属層３８および金属層３９のトータルの厚さよりも厚く設けられる。絶縁層３７は、第１延在部３７ａと第２延在部３７ｂとを含む。
第１延在部３７ａは、Ｚ方向において、金属層３５の外縁３５ｅと金属層３８の外縁３８ｅとの間に位置する。また、第１延在部３７ａは、Ｚ方向において、金属層３５の外縁３５ｅと金属層３９の外縁３９ｅとの間に位置する。第２延在部３７ｂは、Ｚ方向において、電極３３と金属層３５の外縁３５ｅとの間に位置する。
絶縁膜３７は、金属層３５の外縁３５ｅの上面に接する表面３７Ｓ１と、金属層３９の外縁３９ｅに接する表面３７Ｓ２と、金属層３８の外縁３８ｅに接する表面３７Ｓ３と、を含む。表面３７Ｓ３は、表面３７Ｓ１と表面３７Ｓ２との間に位置する。
次に、図３（ａ）～図４（ｂ）を参照して、図２に示す電極構造を形成する方法を説明する。図３（ａ）～図４（ｂ）は、実施形態に係る半導体素子１の製造過程を順に示す模式断面図である。
図３（ａ）に示すように、金属層３５および絶縁層３７を電極３３の上に形成する。絶縁層３７は、電極３３を露出させた、開口３７ｆを有する。金属層３５は、例えば、ニッケルを主成分とする金属の無電解めっきにより形成される。金属層３５は、絶縁層３７をマスクとして電極３３の上に選択的に形成される。金属層３５は、絶縁層３７の内周面に接するように形成させる。金属層３５の材料は、ニッケル・リン合金、ニッケル・ホウ素合金、ニッケル・コバルト・タングステン・リン合金などであっても良い。また、金属層３５の材料は、銅を主成分とした材料であっても良い。
絶縁層３７には、ガラス転移点を有する絶縁材を用いる。絶縁層３７は、例えば、シロキサンを含み、スピンコート法を用いて電極３３の上に形成される。開口３７ｆは、例えば、フォトリソグラフィにより形成されたエッチングマスク（図示しない）を用いて、絶縁層３７を選択エッチングすることにより形成される。また、絶縁層３７は、例えば、スクリーン印刷などにより形成されても良い。
絶縁層３７の開口３７ｆは、電極３３の表面から上方に向かって開口幅が広くなるように形成される。このため、金属層３５の外縁３５ｅは、絶縁層３７のエッジ上に広がるように形成される。すなわち、金属層３５の外縁３５ｅと電極３３との間に、絶縁層３７の第２延在部３７ｂが形成される。
図３（ｂ）に示すように、金属層３５の外縁３５ｅを覆うように、絶縁層３７を変形させる。絶縁層３７は、そのガラス転移点よりも高い温度に加熱される。絶縁層３７の加熱には、例えば、リフロー方式を用いる。これにより、金属層３５の外縁３５ｅの上に、絶縁層３７の第１延在部３７ａが形成される。絶縁層３７は、金属層３５の外縁３５ｅの上面に接する表面３７Ｓ１を有するように形成される。
絶縁層３７に用いられる絶縁材は、１２０℃～３５０℃の温度範囲にガラス転移点を有することが好ましい。ガラス転移点が１２０℃未満である場合、例えば、開口３７ｆを形成するリソグラフィ過程における熱により、絶縁層３７が変形することがある。また、リフロー後の処理、例えば、ウェーハを乾燥させる過程において、絶縁層３７の再度の熱変形を避けることも難しくなる。一方、金属層３５にニッケルを用いた場合、３５０℃よりも高い温度で相転移をともなった結晶化が生じる。これらの熱変形もしくは熱変性を避けるために、１２０℃以上、３５０℃以下の温度範囲において、絶縁層３７を熱変形させることが望ましい。
図４（ａ）に示すように、金属層３５の上に金属層３８を形成する。金属層３８は、例えば、無電解めっきを用いて選択的に形成される。金属層３８は、例えば、パラジウム層である。また、金属層３８の材料は、金、ニッケル、タングステンまたはリンなどを含む金属であっても良い。金属層３８の外縁３８ｅは、絶縁層３７の第１延在部３７ａに接する。絶縁層３７は、金属層３８の外縁３８ｅに接する表面３７Ｓ３を有する。
図４（ｂ）に示すように、金属層３８の上に金属層３９を形成する。金属層３９は、例えば、無電解めっきを用いて選択的に形成される。金属層３９は、例えば、金（Ａｕ）層である。金属層３９の材料は、例えば、パラジウムを含む金属であっても良い。金属層３９の外縁３９ｅは、絶縁層３７の第１延在部３７ａに接する。絶縁層３７は、金属層３９の外縁３９ｅに接する表面３７Ｓ２を有する。
上記の製造過程は例示であり、これに限定される訳ではない。例えば、金属層３８を形成することなく、金属層３５の上に金属層３９を直接形成しても良い。
図５は、比較例に係る半導体素子２の電極構造を示す模式断面図である。半導体素子２の製造過程では、絶縁層３７を変形させる熱処理を実施しない。このため、金属層３８および金属層３９は、金属層３５と同様に絶縁層３７のエッジ３７ｅに沿って広がるように形成される。
例えば、金属層３９を形成する際に用いられる金めっき液は、ニッケルを含む金属層３５と反応し、金属層３５を腐食もしくは溶解する。金属層３５および金属層３８を形成した後、金属層３９を形成するためにウェーハをめっき液に浸漬すると、金属層３５および３８と絶縁層３７との界面に沿ってめっき液が浸潤し、金属層３５と絶縁層３７との間に隙間ＶＳＬを生じさせる場合がある。さらに、金属層３８がパラジウムを含む場合には、めっき液中の金錯体とパラジウムとの間の電子授受が生じ難いことに起因して、ニッケルの腐食が促進される場合がある。
したがって、金属層３９を厚く形成するために、ウェーハをめっき液に浸漬する時間を長くすると、絶縁層３７と金属層３５との間の隙間ＶＳＬが広くなる。また、めっき液が電極３３に到達すると、電極３３も浸食される。このため、電極３３と金属層３５との間に空洞ＶＳＰが形成される場合もある。その結果、半導体装置１００の電気特性および信頼性を劣化させることがある。
これに対し、実施形態に係る半導体素子１では、金属層３５を形成した後に、絶縁層３７を加熱し、金属層３５の外縁３５ｅの上面を覆うように変形させる（図２参照）。これにより、金属層３８の外縁３８ｅの上面から絶縁層３７に沿って電極３３に至る沿面距離が長くなり、めっき液の浸潤が電極３３にまで至ることを回避できる。その結果、半導体装置１００の電気特性の劣化を防ぎ、信頼性を向上させることができる。
図６は、実施形態の第１変形例に係る半導体素子３の電極構造を示す模式断面図である。この例では、絶縁層３７の第１延在部３７ａは、金属層３８の外縁３８ｅの上に設けられる。一方、絶縁層３７の第２延在部３７ｂは、Ｚ方向において、電極３３と金属層３５の外縁３５ｅとの間に位置する。また、第２延在部３７ｂは、Ｚ方向において、電極３３と金属層３８の外縁３８ｅとの間に位置する。
絶縁層３７は、金属層３９の外縁３９ｅに接する表面３７Ｓ２と、金属層３８の外縁３８ｅの上面に接する表面３７Ｓ３と、を含む。表面３７Ｓ２は、表面３７Ｓ３に隣接する位置に設けられる。
半導体素子３では、金属層３８の上面から絶縁層３７に沿って電極３３に至る沿面距離が長くなると共に、金属層３８の上面から金属層３５に至る、絶縁層３７と金属層３８と間の界面も長くなる。これにより、めっき液の浸潤を抑制すると共に、金属層３５とめっき液との接触を遅らせて腐食溶解反応を抑制することもできる。
図７（ａ）および（ｂ）は、実施形態の第１変形例に係る半導体素子３の製造過程を順に示す模式断面図である。
図７（ａ）に示すように、絶縁層３７をマスクとして、金属層３５および金属層３８を電極３３の上に選択的に形成する。金属層３５および金属層３８は、例えば、無電解めっきにより形成される。
図７（ｂ）に示すように、絶縁層３７をガラス転移点よりも高い温度に加熱し、金属層３８の外縁３８ｅを覆うように変形させる。絶縁膜３７は、金属層３８の外縁３８ｅの上面に接する表面３７Ｓ３を含む。
続いて、金属層３８の上に金属層３９（図６参照）を形成する。金属層３９は、絶縁層３７をマスクとして、例えば、無電解めっきにより選択的に形成される。絶縁膜３７は、金属層２９の外縁３９ｅに接する表面３７Ｓ２を含む。
図８は、実施形態の第２変形例に係る半導体素子４の電極構造を示す模式断面図である。この例では、絶縁層３７は、第１延在部３７ａおよび第２延在部３７ｂに加えて第３延在部３７ｃをさらに有する。金属層３８の外縁３８ｅおよび金属層３９の外縁３９ｅは、それぞれステップ状に設けられる。
図８に示すように、第１延在部３７ａは、Ｚ方向において、金属層３８の外縁３８ｅと金属層３９の外縁３９ｅとの間に位置する。第２延在部３７ｂは、Ｚ方向において、電極３３と金属層３５の外縁３５ｅとの間に位置する。第３延在部３７ｃは、Ｚ方向において、金属層３８の外縁３８ｅと金属層３５の外縁３５ｅとの間に位置する。
絶縁層３７は、金属層３５の外縁３５ｅの上面に接する表面３７Ｓ１と、金属層３９の外縁３９ｅに接する表面３７Ｓ２と、金属層３８の外縁３８ｅの上面に接する表面３７Ｓ３と、を含む。表面３７Ｓ３は、表面３７Ｓ１と表面３７Ｓ２との間に位置する。
図８に示す電極構造は、２段階の熱処理により形成される。例えば、第１ステップとして、金属層３５を形成した後に、絶縁層３７をガラス転移点よりも高い温度に加熱し、金属層３５の外縁３５ｅを覆うように変形させる。さらに、第２ステップとして、金属層３８を形成した後に、絶縁層３７をガラス転移点よりも高い温度に再度加熱し、金属層３８の外縁３８ｅを覆うように変形させる。
このように、金属層３８の外縁３８ｅおよび金属層３９の外縁３９ｅをステップ状に設けることにより、金属層３８の外縁３８ｅの上面から電極３３に至る、絶縁層３７に沿った沿面距離をさらに長くすることができる。また、金属層３８の上面から金属層３５に至る、絶縁層３７と金属層３８との界面も長くなる。これにより、めっき液の浸潤を抑制すると共に、金属層３５とめっき液との腐食溶解反応を抑制することができる。
図９は、実施形態の第３変形例に係る半導体素子５の電極構造を示す模式断面図である。この例では、絶縁層３７は、金属層３５の外縁３５ｅを覆う第１延在部３７ａを有するが、電極３３と外縁３５ｅとの間に位置する第２延在部３７ｂを有さない。
図９に示すように、第１延在部３７ａは、Ｚ方向において、金属層３５と金属層３８の外縁３８ｅとの間に位置する部分を含む。また、第１延在部３７ａは、Ｚ方向において、金属層３５と金属層３９の外縁３９ｅとの間に位置する部分を含む。
絶縁層３７は、金属層３５の外縁３５ｅの上面に接する表面３７Ｓ１と、金属層３９の外縁３９ｅに接する表面３７Ｓ２と、金属層３８の外縁３８ｅに接する表面３７Ｓ３と、を含む。表面３７Ｓ３は、表面３７Ｓ１と表面３７Ｓ２との間に位置する。
図１０（ａ）および（ｂ）は、実施形態の第３変形例に係る半導体素子５の製造過程を示す模式断面図である。
図１０（ａ）に示すように、電極３３の上に絶縁層３７を形成した後に、金属層３５を電極３３上に選択的に形成する。この例では、絶縁層３７は、電極３３から上方に、Ｘ方向およびＹ方向の幅が狭くなる開口３７ｆを有する。開口３７ｆは、所謂、逆テーパ形状を有するように形成される。金属層３５は、開口３７ｆの内壁に沿った外縁３５ｅを有する。
図１０（ｂ）に示すように、絶縁層３７をガラス転移点よりも高い温度に加熱し、金属層３５の外縁３５ｅを覆うように変形させる。続いて、金属層３８および金属層３９を、例えば、無電解めっきにより選択的に形成する（図９参照）。絶縁層３７は、金属層３５の外縁３５ｅの上面に接する表面３７Ｓ１を有するように形成される。
このように、第２延在部３７ｂを設けることなしに、金属層３８から電極３３に至る、金属層３５と絶縁層３７との間の界面の長さを長くすることができる。この例では、絶縁層３７のＺ方向の厚さを厚くすることにより、金属層３５と絶縁層３７との間の界面の長さを、図２に示す半導体素子１および図４に示す半導体素子２における界面の長さよりも長く形成することができる。これにより、半導体素子５では、めっき液の浸潤が電極３３にまで至る時間をより長くし、半導体装置１００の電気特性および信頼性の劣化を抑制できる。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１、２、３、４、５…半導体素子、 １０…実装基板、 １１…マウントパッド、 １３…配線、 １５、２３、２５…接続部材、 ２０…接続導体、 ３０…半導体部、 ３１、３３…電極、 ３５、３８、３９…金属層、 ３５ｅ、３８ｅ、３９ｅ…外縁、 ３７…絶縁層、 ３７ａ…第１延在部、 ３７ｂ…第２延在部、 ３７ｃ…第３延在部、 ３７ｅ…エッジ、 ３７ｆ…開口、 ３７Ｓ１、３７Ｓ２、３７Ｓ３…表面、 １００…半導体装置、 ＶＳＬ…隙間、 ＶＳＰ…空洞

Claims (8)

  1. 半導体部と、
    前記半導体部上に設けられ、前記半導体部に電気的に接続された電極と、
    前記電極の表面上に選択的に設けられた第１金属層と、
    前記電極上において前記第１金属層を囲み、前記第１金属層の外縁の上面に接する第１表面を有する絶縁層と、
    前記第１金属層上に設けられた第２金属層であって、前記絶縁層の前記第１表面に連続する前記絶縁層の第２表面に接する外縁を有する第２金属層と、
    前記第１金属層および前記第２金属層の間に設けられた第３金属層と、
    を備え、
    前記第３金属層の外縁および前記第３金属層の前記外縁の上面は、前記絶縁層の前記第１表面と前記第２表面との間に位置する第３表面に接した半導体装置。
  2. 前記絶縁層は、前記電極の前記表面に垂直な方向において、前記第１金属層の前記外縁と前記電極との間に位置する延在部を含む請求項１記載の半導体装置。
  3. 前記電極の前記表面に垂直な方向における前記絶縁膜の厚さは、前記電極の前記表面から前記第２金属層の上面に至る前記方向に沿った距離よりも厚い請求項１または２に記載の半導体装置。
  4. 半導体部と、
    前記半導体部上に設けられ、前記半導体部に電気的に接続された電極と、
    前記電極の表面上に選択的に設けられた第１金属層と、
    前記電極上において前記第１金属層を囲み、前記電極と前記第１金属層の外縁との間に位置する延在部を有する絶縁層と、
    前記第１金属層上に設けられ、前記絶縁層に接する外縁を有する第２金属層と、
    前記第１金属層と前記第２金属層との間に設けられた第３金属層と、
    を備え、
    前記絶縁層は、前記第１金属層の前記外縁および前記第３金属層の外縁を覆う部分を有し、前記第３金属層の前記外縁の上面に接する表面を含む半導体装置。
  5. 半導体部上に設けられ、前記半導体部に電気的に接続された電極上に設けられた絶縁層であって、前記電極の一部を露出させた開口を有し、ガラス転移点を有する材料を含む絶縁層を形成する工程と、
    前記絶縁層の前記開口内において、前記電極の表面に垂直な方向における厚さが前記絶縁層の前記方向の厚さよりも薄い第１金属層を前記電極上に形成する工程と、
    前記絶縁層を前記ガラス転移点よりも高温に加熱し、前記絶縁層の一部が前記第１金属層の外縁部を覆うように、前記絶縁膜を変形させる工程と、
    前記第１金属層の露出された表面上に第２金属層を形成する工程と、
    を備え、
    前記第２金属層の外縁が、前記絶縁層の一部の上に位置するように形成する半導体装置の製造方法。
  6. 前記第１金属層上に第３金属層を形成する工程をさらに備え、
    前記第２金属層は、前記第３金属層の上に形成される請求項５記載の半導体装置の製造
    方法。
  7. 前記第３金属層は、前記絶縁層を前記ガラス転移点よりも高温に加熱した後に形成される請求項６記載の半導体装置の製造方法。
  8. 前記絶縁層は、前記第３金属層を前記第１金属層上に形成した後において、前記ガラス転移点よりも高温に加熱される請求項６記載の半導体装置の製造方法。
JP2019044019A 2019-03-11 2019-03-11 半導体装置およびその製造方法 Active JP7235541B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2019044019A JP7235541B2 (ja) 2019-03-11 2019-03-11 半導体装置およびその製造方法
CN201910676240.6A CN111682005B (zh) 2019-03-11 2019-07-25 半导体装置及其制造方法
US16/540,159 US10998257B2 (en) 2019-03-11 2019-08-14 Semiconductor device and method of manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019044019A JP7235541B2 (ja) 2019-03-11 2019-03-11 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2020150030A JP2020150030A (ja) 2020-09-17
JP7235541B2 true JP7235541B2 (ja) 2023-03-08

Family

ID=72423424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019044019A Active JP7235541B2 (ja) 2019-03-11 2019-03-11 半導体装置およびその製造方法

Country Status (3)

Country Link
US (1) US10998257B2 (ja)
JP (1) JP7235541B2 (ja)
CN (1) CN111682005B (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109380A (ja) 2009-12-25 2010-05-13 Toshiba Corp 微粒子膜形成装置・形成方法、ならびに半導体装置およびその製造方法
JP2016111290A (ja) 2014-12-10 2016-06-20 三菱電機株式会社 半導体素子、半導体装置および半導体素子の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003338516A (ja) 2002-05-20 2003-11-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4604641B2 (ja) * 2004-10-18 2011-01-05 株式会社デンソー 半導体装置
JP2010263137A (ja) 2009-05-11 2010-11-18 Renesas Electronics Corp 半導体装置及びその製造方法
JP5518211B2 (ja) * 2010-11-16 2014-06-11 三菱電機株式会社 半導体素子、半導体装置及び半導体素子の製造方法
WO2015107796A1 (ja) 2014-01-20 2015-07-23 三菱電機株式会社 半導体素子およびその製造方法、ならびに半導体装置
JP7180392B2 (ja) * 2019-01-11 2022-11-30 株式会社デンソー 半導体装置及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109380A (ja) 2009-12-25 2010-05-13 Toshiba Corp 微粒子膜形成装置・形成方法、ならびに半導体装置およびその製造方法
JP2016111290A (ja) 2014-12-10 2016-06-20 三菱電機株式会社 半導体素子、半導体装置および半導体素子の製造方法

Also Published As

Publication number Publication date
JP2020150030A (ja) 2020-09-17
US10998257B2 (en) 2021-05-04
CN111682005A (zh) 2020-09-18
CN111682005B (zh) 2023-10-27
US20200294897A1 (en) 2020-09-17

Similar Documents

Publication Publication Date Title
JP5776701B2 (ja) 半導体装置、および、半導体装置の製造方法
JP5168870B2 (ja) 半導体装置
JP6206494B2 (ja) 半導体装置
KR20160132499A (ko) 반도체장치 및 반도체장치의 제조방법
JP6305176B2 (ja) 半導体装置及び製造方法
JP4967277B2 (ja) 半導体装置およびその製造方法
JP4967701B2 (ja) 電力半導体装置
US20170194296A1 (en) Semiconductor module
JP6448418B2 (ja) 電力用半導体装置
JP6043049B2 (ja) 半導体装置の実装構造及び半導体装置の実装方法
JP2007095984A (ja) 半導体モジュール
JP7088224B2 (ja) 半導体モジュールおよびこれに用いられる半導体装置
JP7235541B2 (ja) 半導体装置およびその製造方法
JP5579148B2 (ja) 電力用半導体装置
JP2016111111A (ja) 半導体装置
JP2005183568A (ja) 電力用半導体装置
WO2020189508A1 (ja) 半導体モジュールおよびこれに用いられる半導体装置
JP2013506310A (ja) 回路装置およびその製造方法
JP2009164511A (ja) 半導体装置およびその製造方法
JP7189846B2 (ja) 半導体装置の製造方法および金属の積層方法
WO2021240944A1 (ja) 半導体装置
JP7294068B2 (ja) ターミナル、および、その製造方法
WO2023095681A1 (ja) 半導体装置
JP2024038590A (ja) 半導体装置および半導体装置の製造方法
CN117083708A (zh) 半导体装置及半导体装置的制造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210715

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220602

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220622

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220722

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20221201

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230104

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230126

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230224

R150 Certificate of patent or registration of utility model

Ref document number: 7235541

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150