JP2005183568A - 電力用半導体装置 - Google Patents
電力用半導体装置 Download PDFInfo
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- JP2005183568A JP2005183568A JP2003420488A JP2003420488A JP2005183568A JP 2005183568 A JP2005183568 A JP 2005183568A JP 2003420488 A JP2003420488 A JP 2003420488A JP 2003420488 A JP2003420488 A JP 2003420488A JP 2005183568 A JP2005183568 A JP 2005183568A
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Abstract
【解決手段】 電力用半導体装置が、制御配線と制御配線を挟んで対向配置された外部電極とを表面に備えた半導体素子と、制御配線を覆う絶縁層と、外部電極上に設けられた接続材料と、接続材料に接続された引き出し電極とを含む。引き出し電極5Aは、空隙部11を挟んで絶縁層9Bを覆う。絶縁層と外部電極とを覆う金属膜10Aを含むものであっても良い。
【選択図】図4
Description
板状部材を半導体素子の電極に接合するためには、板状部材と電極とをはんだで接合するとともに、電極以外の絶縁層で覆われた部分にも、はんだに対する濡れ性の良い金属を設け、その上に板状部材をはんだで接合する(例えば、特許文献1参照)。
図1は、全体が100で表される、本発明の実施の形態1にかかる電力用半導体装置の断面図であり、図2は、電力用半導体装置100のIGBT2近傍の斜視図である。
電力用半導体装置100はブロック1を含む。ブロック1は、例えば、厚さ3mmの銅からなる。ブロック1の上には、IGBT2とダイオード3とが、はんだ4Aにより固定されている。IGBT2は、例えば、厚さ0.4mm、縦横がそれぞれ15mmであり、ダイオード3は、例えば、厚さ0.3mm、縦11mm×横17mmである。また、はんだ4Aには、例えば、厚さ0.15mmのSn−Ag−Cu系はんだが用いられる。
ブロック1は、IGBT2およびダイオード3からの放熱手段と、両素子の裏面側配線の双方を兼ねる。
図3では、エミッタ電極10がゲート配線9Aを挟んで対向配置されているが、対向配置された2つのエミッタ電極10は連結されていても良い。即ち、本願発明は、2つのエミッタ電極10が互いに連結しているか否かに関わらず、ゲート配線9Aが2つのエミッタ電極10間を分割するように配置された構造に適用される。
一方、絶縁層9Bははんだ4Bと濡れを生じないため、絶縁層9Bに上には空隙11が形成される。
なお、ここでは図示しないが、ダイオード3の表面にも同様に、はんだ4Bが濡れるように金属層が形成されている。
なお、はんだ4Bの膜厚を薄くした場合や、引き出し電極5Aの空隙に対応する部分に高分子材料等のはんだに対してぬれを生じない材料でコーティングした場合には、空隙11の上部にははんだ4Bが存在せず、空隙11が直接引き出し電極部5Aに接するようになる。
試験に用いたサンプルの断面形状は、図4とほぼ同様であり、半導体チップに対して、リード5として厚さ0.2mmの銅板をはんだで接合したものを用いる。空隙11を有するサンプル(空隙あり)は、図4の構造と同様にゲート配線9Aを覆うように絶縁層9Bを形成することにより作製する。一方、空隙を有しないサンプルは、絶縁層9Bの上にもはんだの濡れる金属膜を形成することにより作製する。
図5の結果から、空隙11を設けた本実施の形態にかかる構造では、温度サイクルによる破損が発生せず、信頼性の高い電力用半導体装置を得ることができることがわかる。
また、絶縁層の剛性を下げても充分な絶縁を得ることが可能となるので、絶縁層の厚さを1μm以下に薄くでき、電力用半導体装置の製造コストを低減できる。
かかる電力用半導体装置110においても、図4の構造を用いて、ゲート配線9Aの上部に空隙11を設けることができる。これにより、熱応力による破壊を防止でき、信頼性の高い電力用半導体装置を得ることができる。
図7は、全体が200で表された、本実施の形態2にかかる電力用半導体装置の部分断面図である。図7中、図1と同一符号は、同一又は相当箇所を示す。
電力用半導体装置200では、絶縁層9B、エミッタ電極10を覆うように、例えば、厚さ4μmのアルミニウムからなる金属層12が形成されている。金属層12は、例えば蒸着法により形成され、エミッタ電極10と電気的に接続されている。
更に、エミッタ電極10の上方の金属層12の表面には、はんだの濡れる金属膜12Aが形成されている。
図8は、全体が300で表される、本発明の実施の形態3にかかる電力用半導体装置のIGBT2近傍の斜視図である。また、図9は、図8の電力用半導体装置300の、VIII−VIII方向の断面図である。図8、9において、図1と同一符号は、同一又は相当箇所を示す。
短冊の幅、短冊間の間隔は、特に限定しないが、成形性の観点からリード5の板厚と同程度以上であることが好ましい。
また、短冊状の引き出し電極部5Aを配置する位置は特に特定しないが、引き出し電極部5Aがゲート配線9Aの上方に位置する場合、エミッタ電極10の上方に位置する場合について、それぞれ以下の実施の形態4、5で説明する。
図10は、全体が400で表される、本発明の実施の形態4にかかる電力用半導体装置の部分断面図である。図10中、図1と同一符号は、同一又は相当箇所を示す。
図11は、全体が500で表される、本発明の実施の形態5にかかる電力用半導体装置の部分断面図である。図11中、図1と同一符号は、同一又は相当箇所を示す。
図11に示すように、本実施の形態にかかる電力用半導体装置500では、ゲート配線9Aの上方にははんだ4Bおよび引き出し電極5Aが無く、空隙13が形成されている。
図12は、本発明の実施の形態6にかかる電力用半導体装置の、IGBT2近傍の斜視図である。図12から明らかなように、本実施の形態では、上述のように引き出し電極部5Aが短冊状に分割されているとともに、その先端部分に、それぞれの短冊状の部分を接続する連結部5Bが設けられている。
そこで、図12のように、短冊状の引き出し電極部5Aの先端を連結部5Bで連結することにより、短冊部分の電流ばらつきを均一化し、IGBT2の局所的な温度上昇を抑制することができる。
Claims (10)
- 制御配線と該制御配線を挟んで対向配置された外部電極とを表面に備えた半導体素子と、
該制御配線を覆う絶縁層と、
該外部電極上に設けられた接続材料と、
該接続材料に接続された引き出し電極とを含み、
該引き出し電極が、空隙部を挟んで該絶縁層を覆うことを特徴とする電力用半導体装置。 - 制御配線と該制御配線を挟んで対向配置された外部電極とを表面に備えた半導体素子と、
該制御配線を覆う絶縁層と、
該絶縁層と該外部電極とを覆う金属膜と、
該金属膜上に設けられた接続材料と、
該接続材料に接続された引き出し電極とを含み、
該引き出し電極が、空隙部を挟んで該絶縁層上の該金属膜を覆うことを特徴とする電力用半導体装置。 - 上記引き出し電極が、短冊状に分割され略平行に配置された櫛歯状電極からなることを特徴とする請求項1または2に記載の電力用半導体装置。
- 制御配線と該制御配線を挟んで対向配置された外部電極とを表面に備えた半導体素子と、
該制御配線を覆う絶縁層と、
該外部電極上に設けられた接続材料と、
該接続材料に接続され、短冊状に分割され略平行に配置された櫛歯状の引き出し電極とを含み、
該引き出し電極が該外部電極の上方に設けられ、該制御配線の上方には空隙部が残されたことを特徴とする電力用半導体装置。 - 制御配線と該制御配線を挟んで対向配置された外部電極とを表面に備えた半導体素子と、
該制御配線を覆う絶縁層と、
該絶縁層と該外部電極とを覆う金属膜と、
該金属膜上に設けられた接続材料と、
該接続材料に接続され、短冊状に分割され略平行に配置された櫛歯状の引き出し電極とを含み、
該引き出し電極が該外部電極の上方に設けられ、該制御配線の上方には空隙部が残されたことを特徴とする電力用半導体装置。 - 制御配線と該制御配線を挟んで対向配置された外部電極とを表面に備えた半導体素子と、
該制御配線を覆う絶縁層と、
該外部電極上に設けられた接続材料と、
該接続材料に接続され、短冊状に分割され略平行に配置された櫛歯状の引き出し電極とを含み、
該引き出し電極が該外部電極の上方に設けられ、該制御配線の上方には緩和層が充填されたことを特徴とする電力用半導体装置。 - 制御配線と該制御配線を挟んで対向配置された外部電極とを表面に備えた半導体素子と、
該制御配線を覆う絶縁層と、
該絶縁層と該外部電極とを覆う金属膜と、
該金属膜上に設けられた接続材料と、
該接続材料に接続され、短冊状に分割され略平行に配置された櫛歯状の引き出し電極とを含み、
該引き出し電極が該外部電極の上方に設けられ、該制御配線の上方には緩和層が充填されたことを特徴とする電力用半導体装置。 - 上記緩和層が、シリコンゲルおよびエポキシ樹脂から選択される材料からなることを特徴とする請求項6または7に記載の電力用半導体装置。
- 上記接続材料が、Sn−Ag系はんだ、Au−Si系はんだ、及びSn−Pb系はんだから選択される一のはんだからなることを特徴とする請求項1〜8のいずれかに記載の電力用半導体装置。
- 更に、上記櫛歯状の引き出し電極の端部に、該引き出し電極を連結する連結部が設けられたことを特徴とする請求項3〜8のいずれかに記載の電力用半導体装置。
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Cited By (9)
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JP2007081155A (ja) * | 2005-09-14 | 2007-03-29 | Hitachi Ltd | 半導体装置 |
JP2007095984A (ja) * | 2005-09-29 | 2007-04-12 | Hitachi Ltd | 半導体モジュール |
JP2007157863A (ja) * | 2005-12-02 | 2007-06-21 | Hitachi Ltd | パワー半導体装置及びその製造方法 |
JP2007266218A (ja) * | 2006-03-28 | 2007-10-11 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2011142360A (ja) * | 2011-04-22 | 2011-07-21 | Renesas Electronics Corp | 半導体装置 |
JP2014057005A (ja) * | 2012-09-13 | 2014-03-27 | Fuji Electric Co Ltd | パワー半導体モジュール |
WO2016071982A1 (ja) * | 2014-11-06 | 2016-05-12 | 三菱電機株式会社 | 半導体モジュールおよび半導体モジュール用の導電部材 |
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Cited By (10)
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JP2007081155A (ja) * | 2005-09-14 | 2007-03-29 | Hitachi Ltd | 半導体装置 |
JP2007095984A (ja) * | 2005-09-29 | 2007-04-12 | Hitachi Ltd | 半導体モジュール |
JP2007157863A (ja) * | 2005-12-02 | 2007-06-21 | Hitachi Ltd | パワー半導体装置及びその製造方法 |
JP2007266218A (ja) * | 2006-03-28 | 2007-10-11 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2011142360A (ja) * | 2011-04-22 | 2011-07-21 | Renesas Electronics Corp | 半導体装置 |
JP2014057005A (ja) * | 2012-09-13 | 2014-03-27 | Fuji Electric Co Ltd | パワー半導体モジュール |
WO2016071982A1 (ja) * | 2014-11-06 | 2016-05-12 | 三菱電機株式会社 | 半導体モジュールおよび半導体モジュール用の導電部材 |
US10475667B2 (en) | 2014-11-06 | 2019-11-12 | Mitsubishi Electric Corporation | Semiconductor module and conductive member for semiconductor module including cut in bent portion |
US11398447B2 (en) | 2017-12-13 | 2022-07-26 | Mitsubishi Electric Corporation | Semiconductor device and method for producing semiconductor device |
CN112331632A (zh) * | 2019-08-05 | 2021-02-05 | 三菱电机株式会社 | 半导体装置 |
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