KR100475718B1 - 반도체 소자의 소자 분리막 형성 방법 - Google Patents
반도체 소자의 소자 분리막 형성 방법 Download PDFInfo
- Publication number
- KR100475718B1 KR100475718B1 KR10-2003-0001801A KR20030001801A KR100475718B1 KR 100475718 B1 KR100475718 B1 KR 100475718B1 KR 20030001801 A KR20030001801 A KR 20030001801A KR 100475718 B1 KR100475718 B1 KR 100475718B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- polysilicon
- silicon substrate
- trench
- oxide
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000002955 isolation Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 150000004767 nitrides Chemical class 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 125000006850 spacer group Chemical group 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 230000002542 deteriorative effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (3)
- 실리콘 기판에 패드 산화막, 폴리실리콘막 및 패드 질화막을 차례로 증착한 후 사진 및 식각 공정을 진행하여 트렌치가 형성될 영역의 실리콘 기판을 노출시키는 단계와,상기 패드 질화막에 대해 습식각을 진행하여 패드 질화막 사이즈를 줄이여 폴리실리콘이 일부 노출되도록 하는 단계와,상기 줄어든 패드 질화막에 의해 드러난 상기 폴리 실리콘 및 실리콘 기판에 산화 공정을 진행하여 폴리실리콘 측벽에 산화막 스페이서를 형성하고 실리콘 기판에 산화막을 형성하는 단계와,상기 산화막이 제거될 때까지 건식 에치백 공정을 진행하여 상기 산화막 스페이서가 라운딩 형상이 되도록 하는 단계와,상기 산화막 스페이서의 라운딩이 그대로 반영되도록 트렌치를 형성하는 단계를포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성 방법.
- 제 1항에 있어서, 상기 에치백 공정은 C/F를 주성분으로 하는 플라즈마를 이용하여 식각 하는 것을 특징으로 하는 STI 에지 모트 방지 방법.
- 제 1항에 있어서, 상기 트렌치 식각 공정은 Cl2를 주성분으로 하는 플라즈마에 HBr 또는 HeO2를 첨가하여 실시하는 것을 특징으로 하는 STI 에지 모트 방지 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0001801A KR100475718B1 (ko) | 2003-01-11 | 2003-01-11 | 반도체 소자의 소자 분리막 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0001801A KR100475718B1 (ko) | 2003-01-11 | 2003-01-11 | 반도체 소자의 소자 분리막 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040064914A KR20040064914A (ko) | 2004-07-21 |
KR100475718B1 true KR100475718B1 (ko) | 2005-03-10 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2003-0001801A KR100475718B1 (ko) | 2003-01-11 | 2003-01-11 | 반도체 소자의 소자 분리막 형성 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100475718B1 (ko) |
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2003
- 2003-01-11 KR KR10-2003-0001801A patent/KR100475718B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR20040064914A (ko) | 2004-07-21 |
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