KR100448309B1 - 반도체기판의정렬마크및그제조방법 - Google Patents

반도체기판의정렬마크및그제조방법 Download PDF

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Publication number
KR100448309B1
KR100448309B1 KR10-1998-0029905A KR19980029905A KR100448309B1 KR 100448309 B1 KR100448309 B1 KR 100448309B1 KR 19980029905 A KR19980029905 A KR 19980029905A KR 100448309 B1 KR100448309 B1 KR 100448309B1
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KR
South Korea
Prior art keywords
insulating film
storage node
semiconductor substrate
alignment mark
pattern
Prior art date
Application number
KR10-1998-0029905A
Other languages
English (en)
Korean (ko)
Other versions
KR19990014171A (ko
Inventor
사또시 마찌다
아끼유끼 미나미
Original Assignee
오끼 덴끼 고오교 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오끼 덴끼 고오교 가부시끼가이샤 filed Critical 오끼 덴끼 고오교 가부시끼가이샤
Publication of KR19990014171A publication Critical patent/KR19990014171A/ko
Application granted granted Critical
Publication of KR100448309B1 publication Critical patent/KR100448309B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Semiconductor Memories (AREA)
KR10-1998-0029905A 1997-07-25 1998-07-24 반도체기판의정렬마크및그제조방법 KR100448309B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21566797A JP3553327B2 (ja) 1997-07-25 1997-07-25 半導体基板のアライメントマーク及びその製造方法
JP97-215667 1997-07-25

Publications (2)

Publication Number Publication Date
KR19990014171A KR19990014171A (ko) 1999-02-25
KR100448309B1 true KR100448309B1 (ko) 2004-11-16

Family

ID=16676184

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1998-0029905A KR100448309B1 (ko) 1997-07-25 1998-07-24 반도체기판의정렬마크및그제조방법

Country Status (4)

Country Link
US (1) US6140711A (ja)
JP (1) JP3553327B2 (ja)
KR (1) KR100448309B1 (ja)
CN (1) CN1131550C (ja)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7522931B2 (en) * 1998-06-05 2009-04-21 Netnumber, Inc. Method and apparatus for accessing a network computer to establish a push-to-talk session
JP3415551B2 (ja) * 2000-03-27 2003-06-09 日本電気株式会社 半導体装置の製造方法
US6630746B1 (en) * 2000-05-09 2003-10-07 Motorola, Inc. Semiconductor device and method of making the same
JP4528464B2 (ja) * 2000-06-08 2010-08-18 株式会社東芝 アライメント方法、重ね合わせ検査方法及びフォトマスク
KR100632627B1 (ko) * 2000-11-17 2006-10-09 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP4766764B2 (ja) * 2001-03-29 2011-09-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP3970546B2 (ja) * 2001-04-13 2007-09-05 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
DE10154981A1 (de) * 2001-10-31 2003-05-15 Infineon Technologies Ag Markenanordnung, Wafer mit mindestens einer Markenanordnung und ein Verfahren zur Herstellung mindestens einer Markenanordnung
KR100850144B1 (ko) * 2006-08-31 2008-08-04 동부일렉트로닉스 주식회사 얼라인먼트 마크 보호 방법
US7973730B2 (en) * 2006-12-29 2011-07-05 Broadcom Corporation Adjustable integrated circuit antenna structure
CN112054010A (zh) * 2020-09-18 2020-12-08 上海华虹宏力半导体制造有限公司 一种半导体对准结构和制造方法及其掩膜版组

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04335571A (ja) * 1991-05-10 1992-11-24 Sony Corp 位置合わせマークの形成方法
JPH0621406A (ja) * 1992-06-29 1994-01-28 Sony Corp Ｓｏｉ構造形成における位置合わせ方法、及び位置合わせ確認方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478782A (en) * 1992-05-25 1995-12-26 Sony Corporation Method bonding for production of SOI transistor device
US5856220A (en) * 1996-02-08 1999-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a double wall tub shaped capacitor
US6307273B1 (en) * 1996-06-07 2001-10-23 Vanguard International Semiconductor Corporation High contrast, low noise alignment mark for laser trimming of redundant memory arrays
US5811331A (en) * 1996-09-24 1998-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Formation of a stacked cylindrical capacitor module in the DRAM technology
US5877064A (en) * 1997-07-15 1999-03-02 Taiwan Semiconductor Manufacturing Co.Ltd Method for marking a wafer
US5915189A (en) * 1997-08-22 1999-06-22 Samsung Electronics Co., Ltd. Manufacturing method for semiconductor memory device having a storage node with surface irregularities
JP3519579B2 (ja) * 1997-09-09 2004-04-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04335571A (ja) * 1991-05-10 1992-11-24 Sony Corp 位置合わせマークの形成方法
JPH0621406A (ja) * 1992-06-29 1994-01-28 Sony Corp Ｓｏｉ構造形成における位置合わせ方法、及び位置合わせ確認方法

Also Published As

Publication number Publication date
CN1211817A (zh) 1999-03-24
KR19990014171A (ko) 1999-02-25
CN1131550C (zh) 2003-12-17
US6140711A (en) 2000-10-31
JPH1145852A (ja) 1999-02-16
JP3553327B2 (ja) 2004-08-11

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