KR100400629B1 - 회로 장치 및 그 제조 방법 - Google Patents

회로 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR100400629B1
KR100400629B1 KR10-2001-0007482A KR20010007482A KR100400629B1 KR 100400629 B1 KR100400629 B1 KR 100400629B1 KR 20010007482 A KR20010007482 A KR 20010007482A KR 100400629 B1 KR100400629 B1 KR 100400629B1
Authority
KR
South Korea
Prior art keywords
conductive
conductive path
circuit element
insulating resin
separation groove
Prior art date
Application number
KR10-2001-0007482A
Other languages
English (en)
Korean (ko)
Other versions
KR20020018929A (ko
Inventor
사까모또노리아끼
고바야시요시유끼
사까모또준지
마시모시게아끼
오까와가쯔미
마에하라에이주
다까하시고우지
Original Assignee
산요덴키가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 산요덴키가부시키가이샤 filed Critical 산요덴키가부시키가이샤
Publication of KR20020018929A publication Critical patent/KR20020018929A/ko
Application granted granted Critical
Publication of KR100400629B1 publication Critical patent/KR100400629B1/ko

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
KR10-2001-0007482A 2000-09-04 2001-02-15 회로 장치 및 그 제조 방법 KR100400629B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000266685A JP3639514B2 (ja) 2000-09-04 2000-09-04 回路装置の製造方法
JP2000-266685 2000-09-04

Publications (2)

Publication Number Publication Date
KR20020018929A KR20020018929A (ko) 2002-03-09
KR100400629B1 true KR100400629B1 (ko) 2003-10-04

Family

ID=18753731

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0007482A KR100400629B1 (ko) 2000-09-04 2001-02-15 회로 장치 및 그 제조 방법

Country Status (4)

Country Link
JP (1) JP3639514B2 (zh)
KR (1) KR100400629B1 (zh)
CN (1) CN1244258C (zh)
TW (1) TW486920B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7799611B2 (en) 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US8236612B2 (en) 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2004071899A (ja) * 2002-08-07 2004-03-04 Sanyo Electric Co Ltd 回路装置およびその製造方法
US20040058478A1 (en) 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
JP4183500B2 (ja) * 2002-12-20 2008-11-19 三洋電機株式会社 回路装置およびその製造方法
JP4135565B2 (ja) * 2003-06-06 2008-08-20 松下電器産業株式会社 電子回路装置およびその製造方法
JP4559777B2 (ja) * 2003-06-26 2010-10-13 株式会社東芝 半導体装置及びその製造方法
JP4446772B2 (ja) * 2004-03-24 2010-04-07 三洋電機株式会社 回路装置およびその製造方法
JP2007116013A (ja) * 2005-10-24 2007-05-10 Renesas Technology Corp 半導体装置及びそれを用いた電源装置
US7663211B2 (en) * 2006-05-19 2010-02-16 Fairchild Semiconductor Corporation Dual side cooling integrated power device package and module with a clip attached to a leadframe in the package and the module and methods of manufacture
WO2008057770A2 (en) 2006-10-27 2008-05-15 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2008124136A (ja) * 2006-11-09 2008-05-29 Denso Corp 半導体パッケージおよびその製造方法
JP5003418B2 (ja) * 2007-11-08 2012-08-15 トヨタ自動車株式会社 半導体装置とその製造方法
JP4800290B2 (ja) * 2007-12-10 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置
KR101064755B1 (ko) * 2008-12-24 2011-09-15 엘지이노텍 주식회사 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법
JP5445368B2 (ja) * 2010-07-13 2014-03-19 サンケン電気株式会社 半導体モジュール及び半導体モジュールの製造方法
WO2014125567A1 (ja) * 2013-02-12 2014-08-21 株式会社メイコー 部品内蔵基板及びその製造方法
US9196577B2 (en) * 2014-01-09 2015-11-24 Infineon Technologies Ag Semiconductor packaging arrangement
CN104392969A (zh) * 2014-10-13 2015-03-04 华东光电集成器件研究所 一种多芯片集成电路抗冲击封装结构
DE102015103779A1 (de) * 2015-03-16 2016-09-22 Pac Tech-Packaging Technologies Gmbh Chipanordnung und Verfahren zur Ausbildung einer Kontaktverbindung
CN107565922B (zh) * 2017-09-13 2020-07-03 湖南省福晶电子有限公司 Smd陶瓷平面基座的制备方法
CN110416101A (zh) * 2019-08-07 2019-11-05 深圳市顺益微电子有限公司 用烧结银浆作为粘接剂的电源模块铜片焊接工艺
JP7157028B2 (ja) 2019-09-17 2022-10-19 アオイ電子株式会社 半導体装置および半導体装置の製造方法
CN114126187B (zh) * 2020-08-26 2024-05-10 宏恒胜电子科技(淮安)有限公司 具有内埋散热结构的线路板及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980012306A (ko) * 1996-07-11 1998-04-30 김광호 수지댐이 형성된 인쇄회로기판 및 그를 이용한 칩 온 보드(Chip On Board)형 반도체 칩 패키지

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980012306A (ko) * 1996-07-11 1998-04-30 김광호 수지댐이 형성된 인쇄회로기판 및 그를 이용한 칩 온 보드(Chip On Board)형 반도체 칩 패키지

Also Published As

Publication number Publication date
JP3639514B2 (ja) 2005-04-20
CN1244258C (zh) 2006-03-01
JP2002076245A (ja) 2002-03-15
KR20020018929A (ko) 2002-03-09
CN1342035A (zh) 2002-03-27
TW486920B (en) 2002-05-11

Similar Documents

Publication Publication Date Title
KR100400629B1 (ko) 회로 장치 및 그 제조 방법
KR100484696B1 (ko) 회로 장치 및 그 제조 방법
KR100386520B1 (ko) 회로 장치의 제조 방법 및 회로 장치
KR100639738B1 (ko) 회로 장치의 제조 방법
KR20050096851A (ko) 회로 장치 및 그 제조 방법
JP3574026B2 (ja) 回路装置およびその製造方法
JP3561683B2 (ja) 回路装置の製造方法
JP2001217372A (ja) 回路装置およびその製造方法
JP3609684B2 (ja) 半導体装置およびその製造方法
JP3691335B2 (ja) 回路装置の製造方法
JP3634709B2 (ja) 半導体モジュール
JP3574025B2 (ja) 回路装置およびその製造方法
JP3668090B2 (ja) 実装基板およびそれを用いた回路モジュール
JP3510839B2 (ja) 半導体装置およびその製造方法
JP2001250884A (ja) 回路装置の製造方法
JP4443190B2 (ja) 半導体装置の製造方法
JP3869633B2 (ja) 半導体装置の製造方法
JP2001250887A (ja) 回路装置の製造方法
JP3691328B2 (ja) 回路装置および回路モジュール
JP3639495B2 (ja) 回路装置の製造方法
JP3778783B2 (ja) 回路装置およびその製造方法
JP2005175509A (ja) 回路装置
JP4036603B2 (ja) 半導体装置およびその製造方法
JP2001250883A (ja) 回路装置の製造方法
JP2001223318A (ja) 回路装置およびその製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120907

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20130903

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20140901

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20150819

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20160818

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20170818

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20180903

Year of fee payment: 16