KR100190367B1 - 소자분리막형성방법 - Google Patents

소자분리막형성방법 Download PDF

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Publication number
KR100190367B1
KR100190367B1 KR1019950003727A KR19950003727A KR100190367B1 KR 100190367 B1 KR100190367 B1 KR 100190367B1 KR 1019950003727 A KR1019950003727 A KR 1019950003727A KR 19950003727 A KR19950003727 A KR 19950003727A KR 100190367 B1 KR100190367 B1 KR 100190367B1
Authority
KR
South Korea
Prior art keywords
film
forming
transition metal
semiconductor substrate
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019950003727A
Other languages
English (en)
Korean (ko)
Other versions
KR960032673A (ko
Inventor
박상훈
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019950003727A priority Critical patent/KR100190367B1/ko
Priority to US08/605,691 priority patent/US5668043A/en
Priority to CN96101498A priority patent/CN1048821C/zh
Priority to TW085102096A priority patent/TW301022B/zh
Priority to JP8038523A priority patent/JP2788889B2/ja
Publication of KR960032673A publication Critical patent/KR960032673A/ko
Application granted granted Critical
Publication of KR100190367B1 publication Critical patent/KR100190367B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
KR1019950003727A 1995-02-24 1995-02-24 소자분리막형성방법 Expired - Fee Related KR100190367B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019950003727A KR100190367B1 (ko) 1995-02-24 1995-02-24 소자분리막형성방법
US08/605,691 US5668043A (en) 1995-02-24 1996-02-22 Method for forming isolated regions in a semiconductor device
CN96101498A CN1048821C (zh) 1995-02-24 1996-02-24 形成半导体器件隔离的方法
TW085102096A TW301022B (enExample) 1995-02-24 1996-02-24
JP8038523A JP2788889B2 (ja) 1995-02-24 1996-02-26 半導体装置における分離形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950003727A KR100190367B1 (ko) 1995-02-24 1995-02-24 소자분리막형성방법

Publications (2)

Publication Number Publication Date
KR960032673A KR960032673A (ko) 1996-09-17
KR100190367B1 true KR100190367B1 (ko) 1999-06-01

Family

ID=19408771

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950003727A Expired - Fee Related KR100190367B1 (ko) 1995-02-24 1995-02-24 소자분리막형성방법

Country Status (5)

Country Link
US (1) US5668043A (enExample)
JP (1) JP2788889B2 (enExample)
KR (1) KR100190367B1 (enExample)
CN (1) CN1048821C (enExample)
TW (1) TW301022B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW365047B (en) * 1996-10-04 1999-07-21 Winbond Electronics Corp Manufacturing method for simultaneously forming trenches of different depths
US6686283B1 (en) * 1999-02-05 2004-02-03 Texas Instruments Incorporated Shallow trench isolation planarization using self aligned isotropic etch
US6306723B1 (en) 2000-03-13 2001-10-23 Chartered Semiconductor Manufacturing Ltd. Method to form shallow trench isolations without a chemical mechanical polish
CN110223916B (zh) * 2019-05-06 2022-03-08 瑞声科技(新加坡)有限公司 一种硅晶片的加工方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766627A (en) * 1980-10-13 1982-04-22 Toshiba Corp Manufacture of semiconductor device
JPS5893220A (ja) * 1981-11-30 1983-06-02 Toshiba Corp 半導体単結晶膜の製造方法
JPH01321629A (ja) * 1988-06-23 1989-12-27 Nec Corp 薄膜形成方法
US5256591A (en) * 1991-01-07 1993-10-26 Gold Star Electron Co., Ltd. Method for forming isolation region in semiconductor device using trench

Also Published As

Publication number Publication date
CN1134038A (zh) 1996-10-23
JP2788889B2 (ja) 1998-08-20
KR960032673A (ko) 1996-09-17
US5668043A (en) 1997-09-16
CN1048821C (zh) 2000-01-26
JPH08264634A (ja) 1996-10-11
TW301022B (enExample) 1997-03-21

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