JPWO2019182681A5 - - Google Patents

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JPWO2019182681A5
JPWO2019182681A5 JP2020550634A JP2020550634A JPWO2019182681A5 JP WO2019182681 A5 JPWO2019182681 A5 JP WO2019182681A5 JP 2020550634 A JP2020550634 A JP 2020550634A JP 2020550634 A JP2020550634 A JP 2020550634A JP WO2019182681 A5 JPWO2019182681 A5 JP WO2019182681A5
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Japan
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photoresist
formation
layer
mask material
memory
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JP2020550634A
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JP7372932B2 (ja
JP2021518670A (ja
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Priority claimed from US15/933,124 external-priority patent/US10312247B1/en
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第１の実施形態の形成を図１Ａ～図１９Ａ、図５Ｃ～図１９Ｃ、図５Ｄ、及び図１５Ｄ～図１９Ｄ（基板のメモリ領域内のメモリセルの形成を示す）並びに図１Ｂ～図１９Ｂ（同じ基板の、論理領域とも呼ばれる周辺領域内の論理デバイスの形成を示す）に示す。プロセスは、シリコン半導体基板１０のメモリ領域部分及び論理領域部分の両方に二酸化ケイ素（酸化物）層１２を形成することによって開始する。酸化物層１２に、窒化ケイ素（窒化物）層１４が形成される。窒化物層１４に、ハードマスク材料１６が形成される。ハードマスク材料１６に、フォトレジスト１８が形成される。次いで、フォトレジストがパターン化され、これには、フォトレジストの部分を選択的に露出させ、フォトレジストの部分を選択的に除去して、下層材料の選択的部分（すなわち、この場合にはハードマスク材料１６のストリップ）を露出させるフォトリソグラフィープロセスが含まれる。結果として得られた構造体を図１Ａ及び図１Ｂに示す。
JP2020550634A 2018-03-22 2019-01-23 ２トランジスタｆｉｎｆｅｔベースのスプリットゲート不揮発性浮遊ゲートフラッシュメモリ及び製造方法 Active JP7372932B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/933,124 US10312247B1 (en) 2018-03-22 2018-03-22 Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication
US15/933,124 2018-03-22
PCT/US2019/014816 WO2019182681A2 (en) 2018-03-22 2019-01-23 Two transistor finfet-based split gate non-volatile floating gate flash memory and method of fabrication

Publications (3)

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JP2021518670A JP2021518670A (ja) 2021-08-02
JPWO2019182681A5 true JPWO2019182681A5 (ja) 2022-01-24
JP7372932B2 JP7372932B2 (ja) 2023-11-01

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JP2020550634A Active JP7372932B2 (ja) 2018-03-22 2019-01-23 ２トランジスタｆｉｎｆｅｔベースのスプリットゲート不揮発性浮遊ゲートフラッシュメモリ及び製造方法

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US (1) US10312247B1 (ja)
EP (1) EP3769338B1 (ja)
JP (1) JP7372932B2 (ja)
KR (1) KR102350218B1 (ja)
CN (1) CN111868928A (ja)
TW (1) TWI693698B (ja)
WO (1) WO2019182681A2 (ja)

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