JPWO2018012510A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JPWO2018012510A1 JPWO2018012510A1 JP2018527616A JP2018527616A JPWO2018012510A1 JP WO2018012510 A1 JPWO2018012510 A1 JP WO2018012510A1 JP 2018527616 A JP2018527616 A JP 2018527616A JP 2018527616 A JP2018527616 A JP 2018527616A JP WO2018012510 A1 JPWO2018012510 A1 JP WO2018012510A1
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
- H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
Description
2 表面
3 裏面
4 ソース電極
6 ドレイン電極
11 半導体層
12 p+型基板
13 n型エピタキシャル層
14 トレンチ
15 裏面
16 第1部分
17 第2部分
18 p+型半導体単位
19 側面
22 MISトランジスタ構造
23 p型ボディ領域
24 n+型ソース領域
25 ゲート絶縁膜
26 ゲート電極
29 n−型ドリフト領域
37 n+型基板
38 p+型エピタキシャル層
43 n型フィールドストップ領域
Claims (24)
- 第1導電型の第1半導体層と、
前記第1半導体層上の第2導電型の第2半導体層と、
前記第2半導体層の前記第1半導体層側と反対側の表面部に形成されたMISトランジスタ構造と、
前記第1半導体層に選択的に形成され、前記第2半導体層に達する底部を有するトレンチと、
前記トレンチに入り込むように前記第1半導体層の裏面上に形成された第1電極とを含み、
前記第2半導体層は、前記トレンチの底部に露出する第1部分および前記第1導電型層に接する第2部分に跨るように第2導電型領域を有しており、
前記第1電極は、少なくとも前記トレンチの底部で前記第2導電型領域とオーミック接触を形成し、前記第1半導体層とオーミック接触を形成しており、
前記第2導電型領域のキャリアライフタイムが0.1μs以上である、半導体装置。 - 前記トレンチは、前記第2半導体層に凹部が形成されるように、前記第1半導体層の厚さよりも大きい深さで形成されている、請求項1に記載の半導体装置。
- 前記第2半導体層は、前記第1部分と前記第2部分との間で連なる平坦な裏面を有している、請求項1に記載の半導体装置。
- 前記トレンチの側部が前記第1半導体層のみで構成されている、請求項1または3に記載の半導体装置。
- 前記MISトランジスタ構造は、第1導電型のボディ領域と、前記ボディ領域の表面部に形成された第2導電型のソース領域と、前記ボディ領域に接するように形成されたゲート絶縁膜と、前記ゲート絶縁膜を挟んで前記ボディ領域に対向するゲート電極とを含み、
前記第2導電型領域は、前記ボディ領域に対して前記第1半導体層側に形成され、前記ボディ領域に接するドリフト領域を含む、請求項1〜4のいずれか一項に記載の半導体装置。 - 前記MISトランジスタ構造が形成された活性領域の周囲の外周領域に形成された表面終端構造をさらに含む、請求項1〜5のいずれか一項に記載の半導体装置。
- 前記第2導電型領域は、前記ドリフト領域と前記第1半導体層との間に形成され、前記ドリフト領域よりも高い濃度を有するフィールドストップ領域をさらに含む、請求項5に記載の半導体装置。
- 前記トレンチは、前記第1半導体層を少なくとも最小幅Wminを有する複数の第1導電型単位に区画しており、
前記第1導電型単位の幅Wminは、前記MISトランジスタ構造の1つのセル幅以上である、請求項1〜7のいずれか一項に記載の半導体装置。 - 前記トレンチは、前記第1半導体層を少なくとも最小幅Wminを有する複数の第1導電型単位に区画しており、
前記第1導電型単位の幅Wminは、前記第2半導体層の厚さの2倍以上である、請求項1〜7のいずれか一項に記載の半導体装置。 - 前記トレンチは、前記第1半導体層を複数の第1導電型単位に区画しており、
前記複数の第1導電型単位は、平面視においてストライプ状に配列されている、請求項1〜7のいずれか一項に記載の半導体装置。 - 前記トレンチは、前記第1半導体層を複数の第1導電型単位に区画しており、
前記複数の第1導電型単位は、平面視においてそれぞれが多角形状に形成され、離散的に配列されている、請求項1〜7のいずれか一項に記載の半導体装置。 - 前記トレンチは、第1半導体層を複数の第1導電型単位に区画しており、
前記複数の第1導電型単位は、平面視においてそれぞれが円形状に形成され、離散的に配列されている、請求項1〜7のいずれか一項に記載の半導体装置。 - 前記第1電極は、前記第1半導体層の前記裏面および前記トレンチの内面に沿うように形成されている、請求項1〜12のいずれか一項に記載の半導体装置。
- 前記第1電極は、前記トレンチに埋め込まれ、さらに前記第1半導体層の前記裏面上に形成されている、請求項1〜12のいずれか一項に記載の半導体装置。
- 前記第1半導体層は、5μm〜350μmの厚さを有している、請求項1〜14のいずれか一項に記載の半導体装置。
- 前記第2半導体層上に形成され、前記MISトランジスタ構造に電気的に接続された第2電極を含む、請求項1〜15のいずれか一項に記載の半導体装置。
- 前記第1半導体層および前記第2半導体層は、ワイドバンドギャップ半導体からなる、請求項1〜16のいずれか一項に記載の半導体装置。
- 第1導電型の第1半導体層の一方表面側に第2導電型の第2半導体層を形成する工程と、
前記第2半導体層の前記第1半導体層側と反対側の表面部に、MISトランジスタ構造を形成する工程と、
前記第1半導体層の前記第2半導体層側と反対側の裏面から選択的にエッチングすることによって、前記第2半導体層に達する底部を有するトレンチを形成する工程と、
少なくとも前記トレンチの底部で前記第2半導体層の第2導電型領域とオーミック接触を形成し、前記第1半導体層とオーミック接触を形成する第1電極を、前記トレンチに入り込むように前記第1半導体層の前記裏面上に形成する工程とを含む、半導体装置の製造方法。 - 前記第2半導体層を形成する工程は、基板として準備された前記第1半導体層上に前記第2半導体層をエピタキシャル成長させる工程を含む、請求項18に記載の半導体装置の製造方法。
- 前記第2半導体層を形成する工程は、
第2導電型基板上に前記第1半導体層をエピタキシャル成長させる工程と、
前記第1半導体層上に前記第2半導体層をエピタキシャル成長させる工程と、
前記第2導電型基板を除去する工程とを含む、請求項18に記載の半導体装置の製造方法。 - 前記トレンチの形成前に、前記第1半導体層を前記裏面側から薄化させる工程を含む、請求項18〜20のいずれか一項に記載の半導体装置の製造方法。
- 前記第1半導体層を薄化させる工程は、研磨によって前記第1半導体層の前記裏面を仕上げる工程を含む、請求項21に記載の半導体装置の製造方法。
- 前記第1電極を形成する工程は、前記第1半導体層の前記裏面上に形成された前記第1電極を、レーザーアニールによってシンター処理する工程を含む、請求項18〜22のいずれか一項に記載の半導体装置の製造方法。
- エピタキシャル成長により形成された第1導電型の第1半導体層と、
前記第1半導体層上にエピタキシャル成長により形成された第2導電型の第2半導体層と、
前記第2半導体層の前記第1半導体層側と反対側の表面部に形成されたMISトランジスタ構造と、
前記第1半導体層に選択的に形成され、前記第2半導体層に達する底部を有するトレンチと、
前記トレンチに入り込むように前記第1半導体層の裏面上に形成された第1電極とを含み、
前記第2半導体層は、前記トレンチの底部に露出する第1部分および前記第1導電型層に接する第2部分に跨るように第2導電型領域を有しており、
前記第1電極は、少なくとも前記トレンチの底部で前記第2導電型領域とオーミック接触を形成し、前記第1半導体層とオーミック接触を形成している、半導体装置。
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