JPWO2016113841A1 - 半導体装置、その製造方法および半導体モジュール - Google Patents
半導体装置、その製造方法および半導体モジュール Download PDFInfo
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Abstract
Description
本発明の実施形態を説明する前に、本発明の前提となる技術を説明する。図14、図15は本発明の前提となる半導体装置の断面図と平面図である。図14に示すように、半導体装置において、同一半導体基板内にIGBT15、サイリスタ素子17、回路領域24およびホール電流回収領域16が形成されている。回路領域24には、PchMOSFET18、NchMOSFET19が形成されている。
図1、図2は本実施の形態1における半導体装置100の断面図と平面図である。図1に示すように、半導体装置100において、同一半導体基板の第1主面側にIGBT15、サイリスタ素子17、回路領域24およびホール電流回収領域16が形成されている。回路領域24には、PchMOSFET18、NchMOSFET19が形成されている。
本実施の形態1における半導体装置100は、第1導電型(即ちN型)のドリフト層(N−ドリフト層4)を備える半導体基板の第1主面側に形成された絶縁ゲート型バイポーラトランジスタ15と、半導体基板の第1主面側に形成されたサイリスタ素子17と、半導体基板の第1主面側に形成された、CMOS回路素子(即ち、PchMOSFET18、NchMOSFET19)を含む回路領域24と、半導体基板の前記第1主面側に形成され、絶縁ゲート型バイポーラトランジスタ15と回路領域24を平面視で隔てるホール電流回収領域16と、半導体基板の第2主面側に形成された第2導電型(即ちP型)の拡散層(即ちP+コレクタ層2)と、を備え、平面視で、絶縁ゲート型バイポーラトランジスタ15の有効面積は、サイリスタ素子17の有効面積以下である。
図3は、本実施の形態2における半導体装置200の断面図である。本実施の形態2における半導体装置200は、半導体装置100(図1)と比較して、P+コレクタ層2の厚みが小さい。それ以外の構成は半導体装置100と同じため説明を省略する。
本実施の形態2における半導体装置200において、拡散層(即ちP+コレクタ層2)は、半導体基板の第2主面側に不純物を注入した後、レーザアニール処理を行うことで形成される。
本実施の形態3における半導体装置300の構成は半導体装置200(図3)と同じであるため、図3を用いて説明する。
本実施の形態3における半導体装置300は、拡散層(即ちP+コレクタ層2)を覆い、半導体基板の第2主面側に露出する金属層1をさらに備え、拡散層と金属層1とはオーミック接触しており、拡散層に注入された第2導電型の不純物の活性化率は1%より小さい。
本実施の形態4における半導体装置400の構成は半導体装置200(図3)と同じであるため、図3を用いて説明する。本実施の形態4においては、半導体基板の厚みをサイリスタ素子17の駆動に必要な通電能力を確保できる限界値まで厚く設計する。これにより、IGBT15およびサイリスタ素子17の機能を損なうことなく、P+コレクタ層2からのホール電流注入量を抑制し、実施の形態2、3よりも回路領域24の寄生動作防止効果を高めることができる。
本実施の形態4における半導体装置400において、半導体基板よりなるドリフト層(即ちN−ドリフト層4)の厚みは、サイリスタ素子17を駆動可能な厚みのうちの上限の厚みである。
図5は、本実施の形態5における半導体装置500の断面図である。半導体装置500において、拡散層(P+コレクタ層2)とN−ドリフト層4との間には、N+バッファ層3が設けられるN+バッファ層3は、N−ドリフト層4よりも不純物濃度が高い。その他の構成は半導体装置200(図3)と同じため、説明を省略する。
前記拡散層と前記ドリフト層の間に形成され、前記ドリフト層と同一の導電型であり、前記ドリフト層よりもキャリア濃度が高いバッファ層(即ちN+バッファ層3)をさらに備える。
図6は、本実施の形態6における半導体装置600の断面図である。図6に示すように、本実施の形態6では、IGBT15またはサイリスタ素子17と平面視で重なり、かつ回路領域24と平面視で重ならない領域に、拡散層(即ちP+コレクタ層2)が形成される。
本実施の形態6における半導体装置600において拡散層(P+コレクタ層2)は、IGBT15又はサイリスタ素子17と平面視で重なり、かつ回路領域24と平面視で重ならない領域に形成される。
図7は、本実施の形態7における半導体装置700の断面図である。半導体装置700においては、半導体装置600(図6)に対して、P+コレクタ層2とN−ドリフト層4との間に、N+バッファ層3をさらに設ける。N+バッファ層3は、P+コレクタ層2と平面視で重なるように設けられる。
本実施の形態における半導体装置700は、バッファ層(即ちN+バッファ層3)をさらに備え、バッファ層は、拡散層(即ちP+コレクタ層2)とドリフト層4の間に、拡散層と平面視で重なるように形成され、ドリフト層と同一の導電型であり、ドリフト層よりもキャリア濃度が高い。
図8は、本実施の形態8における半導体装置800の断面図である。半導体装置800は、実施の形態5の半導体装置500に対してエッジターミネーション領域25をさらに備える。エッジターミネーション領域25は、IGBT15、サイリスタ素子17、回路領域24およびホール電流回収領域16を平面視で囲むように形成される。
本実施の形態8における半導体装置800は、エッジターミネーション領域25をさらに備え、エッジターミネーション領域25は、絶縁ゲート型バイポーラトランジスタ15、サイリスタ素子17、回路領域24およびホール電流回収領域16を平面視で囲み、エッジターミネーション領域25の耐電圧は、回路領域24に形成されたダイオード26の逆耐電圧よりも小さい。
図9は、本実施の形態9における半導体装置900の断面図である。半導体装置900は、半導体装置800(図8)に備わるIGBT15Aは、トレンチ型のゲート27を備える。その他の構成は半導体装置800と同じである。
本実施の形態9における半導体装置900において、絶縁ゲート型バイポーラトランジスタ15Aのゲート27はトレンチ型である。
実施の形態6、実施の形態7に記載の半導体装置600,700において、P+コレクタ層2を形成しない領域(例えば回路領域24と平面視で重なる領域)では、低濃度のN−ドリフト層2と金属層1が接触している。そのため、N−ドリフト層2と金属層1との間にショットキー接合が形成される。ショットキー接合は、PN接合に比べて、逆耐圧が低い。そのため、P+コレクタ層2に負バイアスが印加された場合、ショットキー接合部に負電流が発生する。すると、回路領域24のNchMOSFET19のn+層、p−拡散層5、N−ドリフト層2からなる寄生NPNトランジスタにおいて、p−拡散層5の電位がN−ドリフト層2よりも高くなり、ベース・エミッタ間が順バイアスされる。これにより、寄生トランジスタが動作し、回路が誤動作してしまう可能性がある。
本実施の形態10における半導体装置1000は、回路領域側拡散層(即ちP−コレクタ層28)と、拡散層(P+コレクタ層2)および回路領域側拡散層を覆い、半導体基板の第2主面側に露出する金属層1と、をさらに備え、回路領域側拡散層は、回路領域24と平面視で重なる領域に、金属層1と隣接して設けられ、回路領域側拡散層は、拡散層(即ちP+コレクタ層2)と同一の導電型であり、拡散層よりもキャリア物濃度が低く、ドリフト層(即ちN−ドリフト層4)と回路領域側拡散層とで形成されるダイオード29の逆耐電圧は、ドリフト層と拡散層とで形成されるダイオード30の逆耐電圧よりも小さい。
図11、図12は本実施の形態11における半導体装置1100の断面図と平面図である。
本実施の形態11における半導体装置1100は、金属電極14を備えるボンディングパッド領域32をさらに備え、絶縁ゲート型バイポーラトランジスタ15とサイリスタ素子17とは平面視で100μm以上隔てて配置され、100μm以上隔てられた領域にボンディングパッド領域32が設けられる。
実施の形態1の半導体装置100において、半導体基板としてシリコン基板を用いていた。本実施の形態12における半導体装置においては、半導体基板としてSiC(シリコンカーバイド)半導体基板を用いる。シリコンカーバイドは、シリコンに対して絶縁破壊電界強度が約10倍、バンドギャップ幅が約3倍高い。そのため、半導体基板の薄厚化、エッジターミネーション領域25の縮小による半導体装置の小型化および耐熱性の向上を実現できる。
図13は、本実施の形態13の半導体モジュールの平面図である。本実施の形態の半導体モジュールは、実施の形態1の半導体装置100と、電力用半導体装置35と、絶縁基板38とを備える。半導体装置100は制御ICとして用いられる。電力用半導体装置35は例えば電力用半導体素子としてIGBTを備えている。このIGBTは、例えば、自動車エンジン等の内燃機関用イグニッションシステムにおいて誘導負荷(トランスコイル)を駆動する。絶縁基板38上には、コンデンサ、抵抗素子などの受動素子37が配置されている。
本実施の形態13における半導体モジュールは、半導体装置100と、電力用半導体装置と、受動素子37が配置された絶縁基板38と、を備え、半導体装置100と絶縁基板38とは2本以上の配線39で電気的に接続されており、電力用半導体装置35と38絶縁基板とは2本以上の配線39で電気的に接続されている。また、絶縁基板38、金属板36には、入出力用の配線40が接続される。
Claims (15)
- 第1導電型のドリフト層を備える半導体基板の第1主面側に形成された絶縁ゲート型バイポーラトランジスタ(15)と、
前記半導体基板の前記第1主面側に形成されたサイリスタ素子(17)と、
前記半導体基板の前記第1主面側に形成された、CMOS回路素子を含む回路領域(24)と、
前記半導体基板の前記第1主面側に形成され、前記絶縁ゲート型バイポーラトランジスタ(15)と前記回路領域(24)を平面視で隔てるホール電流回収領域(16)と、
前記半導体基板の第2主面側に形成された第2導電型の拡散層と、
を備え、
平面視で、前記絶縁ゲート型バイポーラトランジスタ(15)の有効面積は、前記サイリスタ素子(17)の有効面積以下である、
半導体装置。 - 前記拡散層は、前記半導体基板の前記第2主面側に不純物を注入した後、レーザアニール処理を行うことで形成される、
請求項1に記載の半導体装置。 - 前記拡散層を覆い、前記半導体基板の前記第2主面側に露出する金属層(1)をさらに備え、
前記拡散層と前記金属層(1)とはオーミック接触しており、
前記拡散層に注入された前記第2導電型の不純物の活性化率は1%より小さい、
請求項1に記載の半導体装置。 - 前記半導体基板よりなるドリフト層の厚みは、前記サイリスタ素子(17)を駆動可能な厚みのうちの上限の厚みである、
請求項1に記載の半導体装置。 - バッファ層をさらに備え、
前記バッファ層は、前記拡散層と前記ドリフト層の間に形成され、前記ドリフト層と同一の導電型であり、前記ドリフト層よりもキャリア濃度が高い、
請求項1に記載の半導体装置。 - 前記拡散層は、前記絶縁ゲート型バイポーラトランジスタ(15)又は前記サイリスタ素子(17)と平面視で重なり、かつ前記回路領域(24)と平面視で重ならない領域に形成される、
請求項1に記載の半導体装置。 - バッファ層をさらに備え、
前記バッファ層は、前記拡散層と前記ドリフト層の間に形成され、前記ドリフト層と同一の導電型であり、前記ドリフト層よりもキャリア濃度が高い、
請求項6に記載の半導体装置。 - エッジターミネーション領域(25)をさらに備え、
前記エッジターミネーション領域(25)は、前記絶縁ゲート型バイポーラトランジスタ(15)、前記サイリスタ素子(17)、前記回路領域(24)および前記ホール電流回収領域(16)を平面視で囲み、
前記エッジターミネーション領域(25)の耐電圧は、前記回路領域(24)に形成されたダイオード(26)の逆耐電圧よりも小さい、
請求項1に記載の半導体装置。 - 前記絶縁ゲート型バイポーラトランジスタ(15)のゲートはトレンチ型である、
請求項1に記載の半導体装置。 - 回路領域側拡散層と、
前記拡散層および前記回路領域側拡散層を覆い、半導体基板の前記第2主面側に露出する金属層(1)と
をさらに備え、
前記回路領域側拡散層は、前記回路領域(24)と平面視で重なる領域に、前記金属層(1)と隣接して形成され、
前記回路領域側拡散層は、前記拡散層と同一の導電型であり、前記拡散層よりも不純物濃度が低く、
前記ドリフト層と前記回路領域側拡散層とで形成されるダイオード(29)の逆耐電圧は、
前記ドリフト層と前記拡散層とで形成されるダイオード(30)の逆耐電圧よりも小さい、
請求項6に記載の半導体装置。 - 金属電極を備えるボンディングパッド領域(32)をさらに備え、
前記絶縁ゲート型バイポーラトランジスタ(15)と前記サイリスタ素子(17)とは平面視で100μm以上隔てて配置され、100μm以上隔てられた領域に前記ボンディングパッド領域(32)が設けられる、
請求項1に記載の半導体装置。 - 前記半導体基板はSiC半導体基板である、
請求項1に記載の半導体装置。 - 請求項1に記載の半導体装置(100)と、
電力用半導体装置(35)と、
受動素子(37)が配置された絶縁基板(38)と、
を備え、
前記半導体装置(100)と前記絶縁基板(38)とは2本以上の配線(39)で電気的に接続されており、
前記電力用半導体装置(35)と前記絶縁基板(38)とは2本以上の配線(39)で電気的に接続されている、
半導体モジュール。 - 請求項1に記載の半導体装置の製造方法であって、
(a)前記半導体基板の前記第2主面側に不純物を注入する工程と、
(b)前記工程(a)の後、前記半導体基板の前記第2主面側にレーザアニール処理を行うことで前記拡散層を形成する工程と、
を備える、
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記半導体装置は、前記拡散層を覆い、前記半導体基板の前記第2主面側に露出する金属層(1)をさらに備え、
(c)前記半導体基板の前記第2主面側に不純物を注入する工程と、
(d)前記工程(c)の後、前記半導体基板の前記第2主面側に前記金属層(1)を形成する工程と、
(e)前記工程(d)の後、前記半導体基板に300℃以上400℃以下で熱処理を行うことで前記拡散層を形成する工程と、
を備える、
半導体装置の製造方法。
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JP6579273B2 (ja) * | 2016-08-12 | 2019-09-25 | 富士電機株式会社 | 半導体集積回路 |
CN110582851B (zh) * | 2017-05-10 | 2023-05-05 | 三菱电机株式会社 | 半导体装置 |
DE102017127848A1 (de) * | 2017-11-24 | 2019-05-29 | Infineon Technologies Ag | Siliziumcarbid-Halbleiterbauelement mit Randabschlussstruktur |
US10685956B2 (en) * | 2017-12-28 | 2020-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device comprising deep counter well and manufacturing mehtod thereof |
JP7065007B2 (ja) * | 2018-10-01 | 2022-05-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN111900087B (zh) * | 2020-08-31 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Igbt器件的制造方法 |
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