JPWO2014041921A1 - 半導体集積回路装置 - Google Patents
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Abstract
Description
実施の形態1にかかる半導体集積回路装置について、上下アームのドライバ機能を一つのシリコンチップに搭載した駆動回路の上アーム出力素子を駆動するハイサイド駆動回路を例に説明する。図1は、実施の形態1にかかる半導体集積回路装置の平面構造を示す平面図である。図2は、図1の切断線A−A’における断面構造を示す断面図である。実施の形態1にかかる半導体集積回路装置を備えた駆動回路の回路構成は、例えば、図9に示す駆動回路111の回路構成(1相)と同様であるため説明を省略する。
次に、実施の形態2にかかる半導体集積回路装置について説明する。図15は、実施の形態2にかかる半導体集積回路装置の平面構造を示す平面図である。図16は、図15の切断線B−B’における断面構造を示す断面図である。実施の形態2にかかる半導体集積回路装置が実施の形態1にかかる半導体集積回路装置と異なる点は、HVJT40にレベルシフタを一体化したセルフシールディング方式のハイサイド駆動回路において、nエピタキシャル領域(n-型領域)12に、HVJT40にハイサイド電源電位VBを印加(ピックアップ)するためのn++高濃度領域(図14の符号12aに相当)が設けられていない点である。
2 n分離領域
2a,12a n++高濃度領域
3 p分離領域
3a,13a,41a p++高濃度領域
10 ハイサイド駆動回路形成領域
11 空洞
12 nエピタキシャル領域
13 p拡散領域
20 MV−PMOS
21 MV−PMOSのp+ソース領域
22 MV−PMOSのp+ドレイン領域
23 MV−PMOSのゲート電極
30 MV−NMOS
31 MV−NMOSのn+ソース領域
32 MV−NMOSのn+ドレイン領域
33 MV−NMOSのゲート電極
40 HVJT
41 pGND領域
43 耐圧領域
50 電極パッド
100 パワーモジュール(インバータ)
101 上アーム出力素子(第1MOSFET,第1IGBT)
102 下アーム出力素子(第2MOSFET,第2IGBT)
103,104 FWD
105 上アーム出力素子ソースと下アーム出力素子ドレインとの接続点
111 駆動回路
112 負荷(モータ)
121 上アーム出力素子がオン状態で、下アーム出力素子がオフ状態となる第1状態
122 上アーム出力素子がオフ状態で、下アーム出力素子がオン状態となる第2状態
GND グランド電位
VB ハイサイド電源電位
Vcc ローサイド電源電位
Vds 主電源
Vs 主電源Vdsの高電位側電位と低電位側電位との間の中間電位
Claims (14)
- 第1導電型半導体基板の表面層に設けられ、回路部が形成され前記回路部の電源の高電圧電位である第1電位が印加される第2導電型領域と、
前記第2導電型領域の内部に設けられ前記回路部を構成し、前記電源の低電圧電位である第2電位が印加される第1導電型ウェル領域と、
前記第1導電型半導体基板の表面層の、前記第2導電型領域の外側に設けられ、前記第2電位よりも低い第3電位が印加される第1導電型低電位領域と、
前記回路部と前記第1導電型低電位領域との間で、かつ前記第1導電型半導体基板と前記第2導電型領域との間に選択的に設けられた空洞と、
前記第2導電型領域を貫通して前記空洞に達する第1導電型領域と、
を備えることを特徴とする半導体集積回路装置。 - 前記第1導電型領域には、前記第2電位が印加されることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記空洞は、前記第1導電型領域から前記第1導電型低電位領域側に向かって延びていることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記空洞は、前記第1導電型領域から前記第1導電型低電位領域にわたって設けられていることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記回路部は、主電源の高電圧電位側に接続された第1素子と、前記第1素子に直列に接続され、かつ前記主電源の低電圧電位側に接続された第2素子と、から構成される出力回路の前記第1素子を駆動し、
前記第2電位は、前記第1素子と前記第2素子との接続点の電位であり、
前記第3電位は、前記主電源の低電圧電位であることを特徴とする請求項1に記載の半導体集積回路装置。 - 前記第1導電型領域と前記第1導電型半導体基板とのパンチスルー耐圧は、前記第1素子がオン状態で、前記第2素子がオフ状態であるときに過渡的に上昇する前記出力回路の前記第1素子と前記第2素子との前記接続点の電位よりも高く設定されていることを特徴とする請求項5に記載の半導体集積回路装置。
- 前記回路部を囲み前記第2導電型領域に配置された耐圧領域と、
前記耐圧領域の内側にドレイン、前記耐圧領域の外側にソースを有するレベルシフタを構成する絶縁ゲート型電界効果トランジスタと、
をさらに備え、
前記空洞は、前記回路部と、前記絶縁ゲート型電界効果トランジスタのドレインとの間に配置されていることを特徴とする請求項1〜6のいずれか一つに記載の半導体集積回路装置。 - 第1導電型半導体基板の表面層に設けられ、回路部が形成され前記回路部の電源の高電圧電位である第1電位が印加される第1の第2導電型領域と、
前記第1の第2導電型領域の内部に設けられ前記回路部を構成し、前記電源の低電圧電位である第2電位が印加される第1導電型ウェル領域と、
前記第1導電型半導体基板の表面層の、前記第1の第2導電型領域の外側に設けられた第2の第2導電型領域と、
前記第1導電型半導体基板の表面層の、前記第2の第2導電型領域の外側に設けられ、前記第2電位よりも低い第3電位が印加される第1導電型低電位領域と、
前記回路部と前記第1導電型低電位領域との間で、かつ前記第1導電型半導体基板と前記第2の第2導電型領域との間に選択的に設けられた空洞と、
前記第1の第2導電型領域と前記第2の第2導電型領域との間に設けられ、前記第2の第2導電型領域を貫通して前記空洞に達する第1導電型領域と、
前記第2の第2導電型領域に配置された、レベルシフタを構成する絶縁ゲート型電界効果トランジスタと、
を備え、
前記第2の第2導電型領域の、前記絶縁ゲート型電界効果トランジスタのドレインと前記第1導電型領域とに挟まれた部分に、前記第1電位に接続された第2導電型高濃度領域が配置されていないことを特徴とする半導体集積回路装置。 - 前記第1導電型領域には、前記第2電位が印加されることを特徴とする請求項8に記載の半導体集積回路装置。
- 前記空洞は、前記回路部と、前記絶縁ゲート型電界効果トランジスタのドレインとの間に配置されていることを特徴とする請求項8に記載の半導体集積回路装置。
- 前記絶縁ゲート型電界効果トランジスタのドレインは、前記第2の第2導電型領域の前記回路部側に配置され、
前記絶縁ゲート型電界効果トランジスタのソースは、前記第2の第2導電型領域の前記第1導電型低電位領域側に配置されていることを特徴とする請求項8に記載の半導体集積回路装置。 - 前記回路部は、主電源の高電圧電位側に接続された第1素子と、前記第1素子に直列に接続され、かつ前記主電源の低電圧電位側に接続された第2素子と、から構成される出力回路の前記第1素子を駆動し、
前記第2電位は、前記第1素子と前記第2素子との接続点の電位であり、
前記第3電位は、前記主電源の低電圧電位であることを特徴とする請求項8に記載の半導体集積回路装置。 - 前記第1導電型領域と前記第1導電型半導体基板とのパンチスルー耐圧は、前記第1素子がオン状態で、前記第2素子がオフ状態であるときに過渡的に上昇する前記出力回路の前記第1素子と前記第2素子との前記接続点の電位よりも高く設定されていることを特徴とする請求項12に記載の半導体集積回路装置。
- 前記第1の第2導電型領域の表面上に絶縁膜を介して設けられた抵抗層をさらに備え、
前記絶縁ゲート型電界効果トランジスタのドレインは、前記第1導電型半導体基板上に配置された配線層を介して前記抵抗層に電気的に接続されていることを特徴とする請求項8〜13のいずれか一つに記載の半導体集積回路装置。
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CN105874597B (zh) | 2014-07-02 | 2019-03-08 | 富士电机株式会社 | 半导体集成电路装置 |
CN107534017B (zh) | 2015-11-19 | 2020-07-14 | 富士电机株式会社 | 半导体装置 |
DE102016119799B4 (de) * | 2016-10-18 | 2020-08-06 | Infineon Technologies Ag | Integrierte schaltung, die einen vergrabenen hohlraum enthält, und herstellungsverfahren |
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US10535730B2 (en) * | 2017-09-28 | 2020-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device |
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