JPWO2013065101A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JPWO2013065101A1 JPWO2013065101A1 JP2013541494A JP2013541494A JPWO2013065101A1 JP WO2013065101 A1 JPWO2013065101 A1 JP WO2013065101A1 JP 2013541494 A JP2013541494 A JP 2013541494A JP 2013541494 A JP2013541494 A JP 2013541494A JP WO2013065101 A1 JPWO2013065101 A1 JP WO2013065101A1
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Abstract
Description
図1(a)は、本発明の実施の形態1である半導体装置の断面図、図1(b)は、同図(a)の一部を示す拡大断面図である。
図9(a)は、本発明の実施の形態2である半導体装置の平面図、図9(b)は、同図(a)のA−A線断面図、図9(c)は同図(b)の一部を拡大した断面図である。
図10(a)は、本発明の実施の形態3である半導体装置の平面図、図10(b)は、同図(a)のB−B線断面図である。
図17(a)は、本発明の実施の形態4である半導体装置の平面図、図17(b)は、同図(a)のC−C線断面図である。
図18に示すように、前記実施の形態1で用いたナノ構造層7は、スプリング形状を持ったナノ構造体9を平面状に配置した構造を有しており、各ナノ構造体9の直径は、上端部、中央部、下端部共に同一である。
前記実施の形態1〜5で用いたナノ構造層7は、スプリング形状を持ったナノ構造体9を平面状に配置した構造を有しているのに対し、本実施の形態のナノ構造層7は、図20に示すように、柱状のナノ構造体9を平面状に配置した構造を有している。このような形状を有するナノ構造体9は、実施の形態1の図3(c)に示したナノ構造層7の製造工程において、半導体チップ1の回転速度を大きくし、スプリングが上下方向に沿って繋がるようにすることで製造することができる。
図21に示すように、本実施の形態のナノ構造層7の特徴は、ナノ構造体9のそれぞれがプレート層6とプレート層8との対向面に対して傾きを持っていることである。このような形状のナノ構造体9を有するナノ構造層7は、次のような方法で製造することができる。
図23に示すように、本実施の形態のナノ構造層7は、プレート層8の上面に対して異なる傾きを持ったジグザグ形状のナノ構造体9を平面状に配置した構造を有している。このような形状のナノ構造体9を有するナノ構造層7は、次のような方法で製造することができる。
図25に示すように、本実施の形態の半導体装置の特徴は、中間プレート層251を介して複数のナノ構造層7が積層されていることが特徴である。図25には、2層のナノ構造層7が積層された例を示したが、ナノ構造層7の形成と中間プレート層25の形成とを交互に繰り返すことにより、3層以上のナノ構造層7を積層することが可能である。また、ナノ構造体9は、スプリング形状を持つものに限定されず、実施の形態6〜8のようなナノ構造体9であってもよい。
図26に示すように、本実施の形態の半導体装置は、回路基板としてのパッケージ基板263の表面に半導体チップ1をフリップチップ接続した構造を有しており、パッケージ基板263と半導体チップ1とを電気的に接続する複数のフリップチップ接続部のそれぞれは、ナノ構造層7を備えている。ナノ構造層7は、導電材料からなる複数の構造体が平面状に配置されたものである。
Claims (16)
- 回路基板と、前記回路基板に実装された半導体チップとを備えた半導体装置であって、
前記半導体チップと前記回路基板との間には、直径または一辺の長さが1μm未満の断面形状を有する複数の構造体が平面状に配置されてなる構造層が設けられていることを特徴とする半導体装置。 - 前記半導体チップと前記構造層との間には、前記複数の構造体のそれぞれの一端が接続された第1プレート層が設けられ、
前記回路基板と前記構造層との間には、前記複数の構造体のそれぞれの他端が接続された第2プレート層が設けられていることを特徴とする請求項1記載の半導体装置。 - 前記複数の構造体のそれぞれは、スプリング形状を有することを特徴とする請求項1記載の半導体装置。
- 前記複数の構造体のそれぞれは、両端部の外形が中央部の外形よりも大きいことを特徴とする請求項3記載の半導体装置。
- 前記複数の構造体のそれぞれは、ジグザク形状を有することを特徴とする請求項1記載の半導体装置。
- 前記複数の構造体のそれぞれは、前記第1プレート層と前記第2プレート層とが対向する面に対して斜め方向に延在していることを特徴とする請求項2記載の半導体装置。
- 前記複数の構造体のそれぞれは、前記第1プレート層と前記第2プレート層とが対向する面に対して垂直方向に延在していることを特徴とする請求項2記載の半導体装置。
- 前記第1プレート層と前記第2プレート層との間に配置された1または複数の中間プレート層を介して前記構造層が多段積層されていることを特徴とする請求項2記載の半導体装置。
- 回路基板と、前記回路基板に実装された半導体チップとを備えた半導体装置であって、
前記半導体チップは、その主面と反対側の裏面が前記回路基板の上面と対向した状態で前記回路基板の上面に実装され、
前記半導体チップの前記主面には、前記半導体チップに形成された素子に電気的に接続された1または複数の端子が形成され、
前記端子には、導電性の接合部材が電気的に接続され、
前記端子と前記接合部材との間には、直径または一辺の長さが1μm未満の断面形状を有する複数の構造体が平面状に配置されてなる構造層が設けられていることを特徴とする半導体装置。 - 前記半導体チップの前記主面には、少なくともゲート端子を含む複数の端子が形成され、
前記ゲート端子に電気的に接続された前記接合部材の高さは、前記ゲート端子の直径または一辺の長さよりも大きいことを特徴とする請求項9記載の半導体装置。 - 前記ゲート端子に電気的に接続された前記接合部材の高さが最大となる位置は、前記半導体チップの上部にあることを特徴とする請求項10記載の半導体装置。
- ベース部材と、前記ベース部材上に搭載された回路基板と、前記回路基板に実装された半導体チップとを備えた半導体装置であって、
前記ベース部材と前記回路基板との間には、絶縁材料からなり、かつ直径または一辺の長さが1μm未満の断面形状を有する複数の構造体が平面状に配置されてなる構造層が設けられていることを特徴とする半導体装置。 - 回路基板と、前記回路基板に実装された半導体チップとを備えた半導体装置であって、
前記半導体チップは、複数のフリップチップ接続部を介して前記回路基板上にフリップチップ接続されており、
前記複数のフリップチップ接続部のそれぞれは、導電材料からなり、かつ直径または一辺の長さが1μm未満の断面形状を有する複数の構造体が平面状に配置されてなる構造層を含むことを特徴とする半導体装置。 - 主面と、前記主面とは反対側の裏面とを有する半導体チップを備え、
前記半導体チップの前記主面には、直径または一辺の長さが1μm未満の断面形状を有する複数の構造体が平面状に配置されてなる構造層が設けられていることを特徴とする半導体装置。 - 回路基板と、前記回路基板に実装された半導体チップとを備え、
前記半導体チップと前記回路基板との間には、直径または一辺の長さが1μm未満の断面形状を有する複数の構造体が平面状に配置されてなる構造層が設けられた半導体装置の製造方法であって、
前記半導体チップの表面に斜め方向から原子を照射して蒸着させることにより、前記複数の構造体を形成する工程を含むことを特徴とする半導体装置の製造方法。 - 前記複数の構造体を形成する際、前記半導体チップをその表面に垂直な軸に対して回転させることにより、前記複数の構造体のそれぞれをスプリング形状にすることを特徴とする請求項15記載の半導体装置の製造方法。
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