CN104903998A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN104903998A
CN104903998A CN201380069778.1A CN201380069778A CN104903998A CN 104903998 A CN104903998 A CN 104903998A CN 201380069778 A CN201380069778 A CN 201380069778A CN 104903998 A CN104903998 A CN 104903998A
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China
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layer
spring
semiconductor device
semiconductor
semiconductor chip
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CN201380069778.1A
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谷江尚史
池田靖
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Hitachi Ltd
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Hitachi Ltd
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Abstract

为了兼顾具有半导体芯片(1)经由接合部件(2a、2b)而与导电部件(3a、3b)电连接的安装构造的半导体装置的热阻的降低与热变形吸收性的提高，接合部件(2a、2b)具有从与半导体芯片(1)接近的一侧起依次具备由具有纳米级尺寸的多个弹簧构成的纳米弹簧层(4)、支撑上述多个弹簧的平面层(5)以及接合层(6)的层叠构造，纳米弹簧层(4)的厚度大于接合层(6)的厚度，接合层(6)的厚度大于平面层(5)的厚度。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造技术，特别涉及适用于在装入了半导体芯片的半导体安装构造中的热阻的降低以及热变形吸收性的提高且有效的技术。
背景技术
作为本技术领域的背景技术，有专利文献1(日本特开2006-287091号公报)、专利文献2(日本特开2003-188209号公报)、专利文献3(日本特开2003-298012号公报)以及非专利文献1。
在专利文献1中，作为“从负担高温高载荷的热压接合工序起，采用以低温低载荷而连接的接合工艺方法，防止由高温所导致的半导体元件的热破坏、由高载荷所导致的电路特性、层间膜裂纹的发生”这样的课题的解决手段，记载了“一种半导体装置，具备在多个衬垫电极部2中形成了金属凸块3的半导体元件1、以及具有布线电极部5的电路安装基板4，在电路安装基板4的布线电极部5上形成有导电性并且具有弹性的导电弹性体6，在金属凸块3刺穿了导电弹性体6的状态下，将半导体元件1安装于电路安装基板4，通过具有绝缘性的粘接层10来将金属凸块3与布线电极部5电连接固定”这样的技术(参照说明书摘要)。
在专利文献2中，作为“提供一种抑制由于半导体芯片与电路基板的热膨胀率差所引起的热应力所导致的连接可靠性的降低，进而适于实现高密度安装的半导体装置及其制造方法”这样的课题的解决手段，记载了“通过实施微加工而得到的加工基板以及图案化技术，来形成控制了形状的微小的导电性连接部，使用它来将半导体芯片与电路基板连接。半导体装置构造为半导体芯片的电极衬垫经由具有至少2个以上的弯折部、弯曲部的导电性连接部而连接到电路基板的电极衬垫，并且在两者之间封入了绝缘性密封部。在该半导体装置中，在施加热应力时，由于导电性连接部分以及绝缘性密封部分发生变形，能够缓和热应力并且提高连接可靠性”这样的技术。
在专利文献3中，作为“提供一种没有所连接的元件材料的耐热性方面的制约、没有由应力所导致的装置的功能的劣化、元件的损伤的担忧、并且没有相邻的连接部相接触而发生相邻的电极间的短路的担忧的半导体装置及其制造方法”这样的课题的解决手段，记载了“固体摄像元件10具有扫描电路部12、光电变换部14、微米弹簧16以及连接层18。微米弹簧16通过金属等将一端紧固到像素电极30之上，并且被形成为向上方弯曲的舌片状，当在容许范围内被压缩了的状态下与光电变换部侧电极42接触，将像素电极30以及光电变换部侧电极42电连接。连接层18在构造上连接扫描电路部12以及光电变换部14”这样的技术。
在非专利文献1中，关于本发明中使用的纳米弹簧层的制造方法以及力学的特性进行了记载。
现有技术文献
专利文献
专利文献1：日本特开2006-287091号公报
专利文献2：日本特开2003-188209号公报
专利文献3：日本特开2003-298012号公报
非专利文献
非专利文献1：Takayuki Kitamura et.al，“FRACTURENANOMECHANICS”，PAN STANFORD PUBLISHING(2011)，ISBN 978-981-4241-83-0
发明内容
装入了半导体芯片的安装构造由于组合多个不同种类的材料来使用，所以伴随着温度变化，产生由各部件的热变形的差异所引起的热应力。另外，伴随着半导体装置的使用环境的多样化，如果扩大被使用的温度区域，则产生的热应力也变大，所以防止由该热应力所导致的半导体装置的可靠性的降低成为课题。特别是，半导体芯片与周边的材料相比，线膨胀系数较小，所以与周边的材料的热变形差更大。因此，在半导体芯片与导电材等其他部件的接合部，要求能够吸收热变形差的变形吸收性。
另外，在半导体装置的动作时，半导体芯片发热。然后，如果伴随着安装密度的增加而发热温度变高，则半导体芯片的温度上升变得显著，存在由该温度上升所导致的半导体芯片的效率降低、由热应力所导致的部件的破损的担忧。因此，关于半导体安装构造，温度上升的抑制、即散热性的提高成为课题。
为了抑制半导体安装构造的温度上升，期望使半导体芯片与其他部件的接合部变薄，使热阻减小。然而，为了提高接合部的热变形吸收性，期望使接合部变厚，所以热阻的降低与热变形吸收性的提高处于权衡的关系。
本发明的目的在于，提供具备能够兼顾热阻的降低与热变形吸收性的提高的安装构造的半导体装置。
根据本说明书的叙述和附图，本发明的上述目的和其他目的以及新的特征将变得明确。
如果简单说明在本申请中所公开的发明中的代表性的发明的概要，则如下所述。
本发明的半导体装置的一种方式具有半导体芯片经由接合部件而与导电部件电连接的安装构造，上述接合部件具有从与上述半导体芯片接近的一侧起依次具备由具有纳米级尺寸的多个弹簧构成的纳米弹簧层、支撑上述多个弹簧的平面层以及接合层的层叠构造，上述纳米弹簧层的厚度大于上述接合层的厚度，上述接合层的厚度大于上述平面层的厚度。
如果简单说明通过在本申请中所公开的发明中的代表性的发明而得到的效果，则如下所述。
通过在将半导体芯片接合到导电部件的接合部件的一部分中配置纳米弹簧层，能够通过纳米弹簧层的变形来吸收半导体芯片与导电部件的热变形差。其结果，不需要使接合层具有热变形吸收性，能够使接合层比纳米弹簧层更薄，所以能够降低热阻。另外，通过使平面层比接合层更薄，从而平面层的抗弯刚度变小，能够追踪纳米弹簧层的变形。进而，由于平面层薄，从而平面层自身的热阻变小，能够有助于半导体装置整体的热阻降低。由此，能够实现兼顾高的热变形吸收性与低热阻的半导体安装构造。
附图说明
图1(a)是作为实施方式1的半导体装置的剖面图，(b)是示出本图(a)的一部分的放大剖面图。
图2(a)是示出作为实施方式1的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图3(a)是示出接着图2(a)的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图4(a)是示出接着图3(a)的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图5(a)是示出接着图4(a)的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图6(a)是示出接着图5(a)的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图7是示出接着图6的半导体装置的制造方法的半导体晶片的剖面图。
图8是示出接着图7的半导体装置的制造方法的半导体晶片以及半导体芯片的立体图。
图9是示出接着图8的半导体装置的制造方法示剖面图。
图10是说明作为实施方式1的半导体装置的效果的图。
图11(a)是作为实施方式2的半导体装置的剖面图，(b)是示出本图(a)的一部分的放大剖面图。
图12(a)是示出作为实施方式2的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图13(a)是示出接着图12(a)的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图14(a)是示出接着图13(a)的半导体装置的制造方法的半导体晶片的整体立体图，(b)是示出本图(a)的一部分的放大剖面图。
图15(a)是作为实施方式3的半导体装置的剖面图，(b)是示出本图(a)的一部分的放大剖面图。
图16(a)是作为实施方式4的半导体装置的剖面图，(b)是示出本图(a)的一部分的放大剖面图。
具体实施方式
以下，根据附图，来详细说明本发明的实施方式。此外，在用于说明实施方式的所有附图中，对具有相同的功能的部件附加相同的符号，省略其重复的说明。另外，在实施方式中，除了在特别需要时，原则上不重复相同或者同样的部分的说明。进而，在说明实施方式的附图中，为了容易理解结构，有时即使是俯视图也附加剖面线，有时即使是剖面图也省略剖面线。
(实施方式1)
图1(a)是作为本发明的实施方式1的半导体装置的剖面图，图1(b)是示出本图(a)的一部分(用四边框包围的区域)的放大剖面图。
如图1(a)所示，作为本实施方式1的半导体装置具有形成有pn节的半导体芯片1的上表面经由接合部件2a而与导电部件3a电连接、下表面经由接合部件2b而与导电部件3b电连接的安装构造。即，在该半导体装置中，从一对导电部件3a、3b的其中一个流入的电流通过半导体芯片1内的二极管元件来整流，从导电部件3a、3b的另一个流出，从而作为二极管发挥功能。
上述半导体芯片1由在半导体制造工艺(前工序)中被赋予二极管功能的单晶硅(Si)构成，关于其尺寸，一边约为6mm，厚度约为0.2mm。另外，构成二极管的电极的一对导电部件3a、3b分别由铜(Cu)等金属板构成。
如图1(b)所示，夹着半导体芯片1的一对接合部件2a、2b中的接合部件2b具有从与半导体芯片1接近的一侧起依次为纳米弹簧层4、平面层5、接合层6的3层构造。虽然省略图示，但接合部件2a也同样地具有从与半导体芯片1接近的一侧起依次为纳米弹簧层4、平面层5、接合层6的3层构造。此外，由镍膜构成的基底层22(后述)介于接合部件2a、2b各自的纳米弹簧层4与半导体芯片1之间，但基底层22的膜厚极薄，所以在图1中未示出。
将半导体芯片1与平面层5连接的纳米弹簧层4具有矩阵状地配置了具有纳米级尺寸、即1μm以下的尺寸的多个线圈状弹簧的构造。例如多个线圈状弹簧分别具有直径约25nm的大致圆形的剖面形状，其外径约为150nm，内径约为100nm，高度约为10μm。另外，相邻的弹簧之间的距离约为50nm，弹簧的材质为镍(Ni)。
这样，关于接合部件2a、2b，由于作为它们的一部分的纳米弹簧层4由多个容易变形的弹簧构成，所以能够通过纳米弹簧层4高效地吸收在动作时产生的半导体芯片1与导电部件3a、3b的热变形差。其结果，能够防止热应力的增大，能够防止由热应力所导致的半导体芯片1的裂缝、接合部件2a、2b的破坏。
作为半导体芯片1的主要材料的硅与作为导电部件3a、3b的主要材料的铜的线膨胀系数差约为13ppm/℃。例如在一边约为6mm的半导体芯片1与导电部件3a、3b的温度变化了200℃的情况下，在半导体芯片1的端部的热变形差约为8μm。为了通过纳米弹簧层4的变形来吸收该热变形差，期望将纳米弹簧层4的厚度设为至少8μm以上。因此，在本实施方式1中，将纳米弹簧层4的厚度设为10μm。
另外，半导体芯片1与平面层5经由由热传导率高的镍(Ni)构成的多个弹簧而连接，从而能够减小半导体芯片1与平面层5之间的热阻，能够将在动作时在半导体芯片1中产生的热高效地传递到导电部件3a、3b而降低半导体芯片1的温度上升。据此，在接合部件2a、2b各自的一部分中具备纳米弹簧层4，从而能够提供降低了热应力、温度上升的高可靠的半导体装置。
平面层5是用于防止构成纳米弹簧层4的纳米级尺寸的多个弹簧变得散乱的支撑部件，例如由镍等导电材料构成，其厚度约为0.5μm。另外，通过与纳米弹簧层4邻接地配置平面层5，能够使与接合层6的接合部位变得平坦，所以能够使接合变得容易，并且防止在接合时接合层6流入纳米弹簧层4的间隙。进而，在作为平面层5的材料而使用镍的情况下，在制造阶段，平面层5的表面不易氧化，所以能够防止表面氧化层妨碍制造。
平面层5的厚度约为0.5μm，与纳米弹簧层4相比较小。这是因为，通过将平面层5设置得较薄，从而减小平面层4的抗弯刚度，提高在经由接合层6而接合平面层5与导电部件3a、3b时的接合性。即，即使当在接合前的平面层5、导电部件3a、3b的表面存在凹凸的情况下，由于纳米弹簧层4的变形而将该凹凸吸收，也能够得到良好的接合。此时，由于平面层5薄、并且抗弯刚度小，能够追踪纳米弹簧层4的变形。进而，由于平面层5薄，从而平面层5自身的热阻变小，能够有助于半导体装置整体的热阻降低。
接合层6由锡(Sn)或者锡合金等焊锡材料构成，其厚度约为5μm。当在接合部件2a、2b的一部分中不具备纳米弹簧层4的情况下，通过接合层6的变形，吸收半导体芯片1与导电部件3的热变形差，所以需要充分地确保接合层6的厚度。另一方面，在接合部件2a、2b的一部分中具备纳米弹簧层4的本实施方式1的构造中，能够通过纳米弹簧层4的变形来吸收半导体芯片1与导电部件3的热变形差。因此，不需要使接合层6吸收该热变形差，所以能够使接合层6的厚度充分地薄。
另外，当在接合部件2a、2b的一部分中不具备纳米弹簧层4的情况下，在接合面的表面凹凸大时，存在产生空隙、未接合部的担忧，所以需要尽可能吸收表面凹凸的接合厚度。另一方面，在接合部件2a、2b的一部分中具备纳米弹簧层4以及比纳米弹簧层4薄的平面层5的本实施方式1的构造中，能够通过纳米弹簧层4的变形来吸收接合面的表面凹凸，所以能够使接合层6薄到μm量级以下的厚度。这样，在具备本实施方式1的构造的半导体装置中，能够使接合层6的厚度比平面层5厚但比纳米弹簧层4薄。据此，使接合层6充分地变薄而使其热阻减小，能够有助于半导体装置整体的热阻降低。
此外，在本实施方式1中，作为纳米弹簧层4、平面层5的材料而使用镍，但也能够使用铜等其他导电材料。在作为纳米弹簧层4、平面层5的材料而使用铜的情况下，接合部件2a、2b的热传导率进一步提高，所以能够进一步降低半导体装置整体的热阻。另外，铜的弹性模量、屈服应力比镍小，所以纳米弹簧层4的变形吸收效果、平面层5的变形追踪性进一步提高。另一方面，与镍相比，铜是更容易氧化的材料，所以有时需要防止氧化处理。进而，在本实施方式1中，作为接合层6的材料使用以锡为主成分的金属，但也能够使用以锌(Zn)、银(Ag)等为主成分的金属。在变更接合层6的材料的情况下，需要与各种材料相符合地优化接合温度、加压等条件。
接下来，参照图2～图9，说明作为本实施方式1的半导体装置的制造方法。此外，在图2～图6的各图中，(a)是半导体晶片的整体立体图，(b)是半导体晶片的表面端部放大剖面图。
首先，如图2所示，准备由多个半导体芯片1构成的半导体晶片21。将由pn节构成的二极管元件形成于该半导体晶片21的各半导体芯片1。
接下来，如图3所示，采用蒸镀法来在半导体晶片21的表面形成由镍膜构成的基底层22。基底层22是出于提高半导体芯片1与纳米弹簧层4的接合强度、向纳米弹簧层4均匀地传递电、热的目的而设置的。基底层22也能够代替蒸镀法而通过镀层法等来形成。另外，当在半导体制造工艺(前工序)中在半导体晶片21的表面设置了金属层的情况下，能够将该金属层用作基底层22，所以能够省略形成基底层22的工序。
接下来，如图4所示，在大致真空的环境下，使半导体晶片21相对于与基底层22的表面垂直的轴而旋转。然后，在该状态下从倾斜向上地配置了的蒸发源(未图示)照射镍原子23，并蒸镀到基底层22的表面。
这样，在针对基底层22的表面从倾斜方向蒸镀镍原子23的情况下，在蒸镀到基底层22的表面的镍原子层中，产生相对于蒸发源而成为阴影的部位，在该阴影的部分，不蒸镀镍原子23。其结果，在基底层22的表面，蒸镀形成在倾斜方向上延伸的大量柱状体。然后，此时通过使半导体晶片21旋转，从而柱状体并非向一个方向延伸而是线圈状地生长。由此，在基底层22的表面形成大量构成纳米弹簧层4的纳米级尺寸的线圈状弹簧。
接下来，在使半导体晶片21的旋转停止之后，如图5所示，通过从纳米弹簧层4的上方蒸镀镍原子24，在纳米弹簧层4的上部形成平面层5。接着，如图6所示，保持半导体晶片21的旋转停止的状态，从平面层5的上方蒸镀锡原子25，从而在平面层5的上部形成接合前的接合层26。
通过到此为止的工序，在半导体晶片21的表面按如下顺序形成基底层22、纳米弹簧层4、平面层5以及接合层26。以下，将这些层的集合称为表面形成层27。
接下来，在使半导体晶片21的表面背面翻转之后，通过实施与上述相同的步骤，如图7所示，在半导体晶片21的背面也形成表面形成层27。
其后，如图8所示，通过对半导体晶片21进行切割·单片化，来取得在两面具备表面形成层27的大量半导体芯片1。
此外，在上述的制造方法中，在对半导体晶片21进行切割·单片化的工序之前，在其两面形成了表面形成层27，但也可以在对半导体晶片21进行切割·单片化之后，通过上述的方法在半导体芯片1的两面形成表面形成层27。此外，在这种情况下，在从倾斜方向蒸镀镍原子23而形成纳米弹簧层4时，需要注意避免在半导体芯片1的侧面蒸镀镍原子23。另一方面，当在切割·单片化之前在半导体晶片21的两面形成表面形成层27的情况下，需要注意避免在对半导体晶片21进行切割·单片化时使表面形成层27破损。因此，期望根据切割的方法等，选择适当的工序。
接下来，如图9所示，用一对导电部件3a、3b来夹入在两面形成了表面形成层27的半导体芯片1，进而在导电部件3a的上部配置在接合时的加压中使用的锤42。此时，为了防止接合前的各部件(半导体芯片1以及导电部件3a、3b)的位置偏移，使用碳制的接合用夹具41a、41b来使各部件的位置对准。
在上述半导体芯片1的两面，形成了接合前的接合层26，所以在使用接合用夹具41a、41b来使各部件的位置对准时不需要另外重叠接合材料，能够提高装配性。
接下来，在使通过接合用夹具41a、41b而位置对准了的各部件暴露于接合前的接合层26的熔点以上的环境下之后进行降温。此时，液化了的接合前的接合层26与构成平面层5的原子、构成导电部件3a、3b的原子发生反应而合金化，在温度下降后，成为合金化了的接合层6。然后，通过该接合层6，将平面层5与导电部件3a以及平面层5与导电部件3b分别接合。在本实施方式1中，合金化了的接合层6是锡与镍、或者锡与铜、或者锡、镍与铜的合金。此外，该接合工序使用回流炉，在大致真空环境下实施。由此，能够降低在接合时产生的未接合部、空隙。最后，去除冷却了的接合用夹具41a、41b以及锤42，从而完成图1所示的作为本实施方式1的半导体装置。
根据上述的制造方法，能够制作密集地配置了纳米级尺寸、即低于1μm的尺寸的弹簧而得到的纳米弹簧层4，所以在构造以及效果上，能够实现与现有技术具有显著的差异的半导体安装构造。
接下来，使用图10来说明在将通过本制造方法制作了的纳米弹簧层4用于半导体安装构造的情况下得到的特征。图10(a)示出了作为现有技术的具有微米级尺寸的尺寸的微米弹簧10，图10(b)示出了将本图(a)所示的微米弹簧10简单地按比例缩小到纳米级尺寸而得到的纳米弹簧11，图10(c)示出了密集地配置了纳米弹簧11而得到的本实施方式1的纳米弹簧层4。
半导体芯片1与导电部件3的热变形差主要通过纳米弹簧层4的剪切变形来吸收，所以将各个弹簧考虑为剪切变形发挥作用的1根针，将微米弹簧10模型化为线径10μm的1根针，将纳米弹簧11模型化为线径10nm的1根针，将纳米弹簧层4模型化为线径10nm的1000000(＝1000×1000)根针。将针的高度以及纳米弹簧层4的厚度全部设为相同的值L。
此时，在针中产生的最大应力(σmax)由下式来表示。
[式1]
σ max = 3 4 E d u L 2
(式中，E为纵向弹性模量，d为线径，u为作用的剪切位移)
根据该式，在纳米弹簧层4与纳米级尺寸的弹簧11中产生的应力相同，但在d为1000倍的微米级尺寸的弹簧10的情况下，产生1000倍的应力，防止其破坏成为课题。
另一方面，热阻(R)由下式来表示。
[式2]
R = 4 L λπd 2 n
(在式中，λ是材料的热传导率，n是根数)
根据该式，纳米弹簧层4与微米级尺寸的弹簧10的热阻相同，但在纳米级尺寸的弹簧11中，热阻为1000000倍，所以半导体芯片1的温度上升变得显著。此外，为了使得微米级尺寸的弹簧10中产生的应力与纳米弹簧层4相同，需要使高度L为32倍，在这种情况下，热阻为32倍。
据此可知，半导体安装构造中要求的兼顾变形吸收与低热阻的功能是在作为现有技术的微米级尺寸的弹簧10、使其简单地按比例缩小而得到的纳米级尺寸的弹簧11中无法实现、而是通过本实施方式1的纳米弹簧层4而首次能够实现的功能。
此外，在本实施方式1中，说明了具有二极管特性的半导体芯片1的安装构造，但当然也能够安装具有其他半导体元件的半导体芯片，在这种情况下，与各半导体芯片的条件相符合地适当设计变更本实施方式1的安装构造即可。
(实施方式2)
图11(a)是作为本发明的实施方式2的半导体装置的剖面图，图11(b)是示出本图(a)的一部分的放大剖面图。
与实施方式1的差异在于构成纳米弹簧层4的弹簧不是线圈状的弹簧而是锯齿状的弹簧这一点。
通过锯齿状的弹簧构成纳米弹簧层4，从而与线圈状的弹簧相比，每根弹簧的占有面积变小，所以能够在每单位面积上配置更多的弹簧。另外，能够缩短将各弹簧笔直地拉长时的长度。
据此，能够进一步降低纳米弹簧层4的热阻，但有时热变形吸收的效率比线圈状弹簧的小。因此，鉴于这些特征，选择弹簧的形状即可。
接下来，参照图12～图14，说明作为本实施方式2的半导体装置的制造方法。此外，实施方式1的差异仅在于纳米弹簧层4的制造方法，所以在这里说明纳米弹簧层4的制造方法。在图12～图14的各图中，(a)是半导体晶片的整体立体图，(b)是半导体晶片的表面端部放大图。
首先，通过与实施方式1同样的方法在半导体晶片21的表面形成基底层22之后，如图12所示，在大致真空的环境下，从半导体晶片21的倾斜向上方向照射镍原子23，并蒸镀到基底层22的表面。此时，与实施方式1的制造方法不同，不使半导体晶片21旋转。
这样，在针对基底层22的表面而从倾斜方向蒸镀镍原子23的情况下，在蒸镀到基底层22的表面的镍原子层，产生相对于蒸发源而成为阴影的部位，在该阴影的部分，不蒸镀镍原子23。其结果，在基底层22的表面，蒸镀形成向倾斜方向延伸的大量柱状体。
接下来，如图13所示，使半导体晶片21相对于与基底层22的表面垂直的轴旋转180°。由此，在基底层22的表面蒸镀形成了的大量柱状体的朝向与图12所示的朝向相反。
接下来，如图14所示，如果在该状态下从半导体晶片21的倾斜向上方向照射镍原子23，则大量柱状体生长为“く”字型。以下，通过将到此为止的工序重复进行所期望的次数，来形成由图11所示的大量锯齿状的弹簧构成了的纳米弹簧层4。
(实施方式3)
图15(a)是作为本发明的实施方式3的半导体装置的剖面图，图15(b)是示出本图(a)的一部分的放大剖面图。
与实施方式1的差异在于将纳米弹簧层4隔着平面层5而多级地层叠这一点。在图15中，示出了层叠了2级的纳米弹簧层4的例子，但通过交替地重复进行纳米弹簧层4的形成和平面层5的形成，也能够层叠3级以上的纳米弹簧层4。另外，构成纳米弹簧层4的弹簧不限定于线圈状的弹簧，也可以是实施方式2那样的锯齿状的弹簧。
一般来说，在将本实施方式3的纳米弹簧层4层叠了n级的情况下，各纳米弹簧层4吸收的变形量降低为1/n，所以能够吸收更大的变形。另一方面，纳米弹簧层4的整体的热阻、电阻为n倍。因此，期望根据所要求的变形吸收能力、热阻、电阻来选定进行层叠的纳米弹簧层4的数量。
(实施方式4)
图16(a)是作为本发明的实施方式4的半导体装置的剖面图，图16(b)是示出本图(a)的一部分的放大剖面图。
与实施方式1的差异在于在构成纳米弹簧层4的多个弹簧的间隙中填充了树脂30这一点。在这样的情况下，根据填充的树脂30的物理参数，能够控制纳米弹簧层4整体的平均刚性。
例如在填充了弹性模量小的树脂的情况下，纳米弹簧层4整体的平均刚性变小，能够降低半导体芯片1、导电部件3a、3b中产生的热应力。另一方面，在填充了弹性模量大的树脂的情况下，纳米弹簧层4整体的平均刚性变大，纳米弹簧层4吸收的热变形差变小，所以能够使纳米弹簧层4变得更薄而降低热阻。因此，鉴于这些效果，选定填充的树脂30的材料即可。
此外，树脂30的填充在接合了半导体芯片1与导电部件3之后进行。这样一来，不会由于树脂30而妨碍基于接合时的纳米弹簧层4的表面凹凸的吸收效果。另外，树脂30既可以在多个弹簧的全部间隙中填充，也可以在多个弹簧的间隙的一部分中填充。
以上，根据实施方式来具体地说明了通过本发明者完成的发明，但本发明不限定于上述实施方式，在不脱离其主旨的范围内，当然能够进行各种变更。
产业上的可利用性
本发明能够应用于具有半导体芯片经由接合部件而与导电部件电连接的安装构造的半导体装置。

Claims (13)

1.一种半导体装置，其特征在于，具有：
半导体芯片；以及
经由接合部件而与所述半导体芯片电连接的导电部件，
所述接合部件从与所述半导体芯片接近的一侧起依次具备由具有纳米级尺寸的多个弹簧构成的纳米弹簧层、支撑所述多个弹簧的平面层以及接合层，
所述纳米弹簧层的厚度大于所述接合层的厚度，
所述接合层的厚度大于所述平面层的厚度。
2.根据权利要求1所述的半导体装置，其特征在于，
构成所述弹簧的材料是镍。
3.根据权利要求1所述的半导体装置，其特征在于，
构成所述弹簧的材料是铜。
4.根据权利要求1所述的半导体装置，其特征在于，
构成所述平面层的材料是镍。
5.根据权利要求1所述的半导体装置，其特征在于，
构成所述平面层的材料是铜。
6.根据权利要求1所述的半导体装置，其特征在于，
构成所述接合层的材料是以锡为主成分的金属。
7.根据权利要求1所述的半导体装置，其特征在于，
所述弹簧具有线圈形状。
8.根据权利要求1所述的半导体装置，其特征在于，
所述弹簧具有锯齿形状。
9.根据权利要求1所述的半导体装置，其特征在于，
在所述纳米弹簧层的至少一部分中填充了树脂。
10.一种半导体装置，其特征在于，具有：
半导体芯片；以及
接合部件，
所述接合部件从与所述半导体芯片接近的一侧起依次具备由具有纳米级尺寸的多个弹簧构成的纳米弹簧层以及支撑所述多个弹簧的平面层，
所述纳米弹簧层的厚度大于所述平面层的厚度。
11.一种半导体装置的制造方法，该半导体装置具有：
半导体芯片；以及
经由接合部件而与所述半导体芯片电连接的导电部件，
所述接合部件从与所述半导体芯片接近的一侧起依次具备由具有纳米级尺寸的多个弹簧构成的纳米弹簧层、支撑所述多个弹簧的平面层以及接合层，
所述半导体装置的制造方法的特征在于，包括：
(a)通过从倾斜方向对半导体晶片的表面照射第1原子来形成所述纳米弹簧层的工序；
(b)在所述工序(a)之后，通过从垂直的方向对半导体晶片的表面照射第2原子来形成所述平面层的工序；
(c)在所述工序(b)之后，通过从垂直的方向对半导体晶片的表面照射第3原子来形成所述粘合层的工序；以及
(d)在所述工序(c)之后，切割所述半导体晶片而单片化成多个所述半导体芯片的工序，
使所述纳米弹簧层的厚度大于所述接合层的厚度，
使所述接合层的厚度大于所述平面层的厚度。
12.根据权利要求11所述的半导体装置的制造方法，其特征在于，
在所述工序(a)中，通过使所述半导体晶片相对于与其表面垂直的轴而旋转，来将构成所述纳米弹簧层的所述弹簧做成线圈形状。
13.根据权利要求11所述的半导体装置的制造方法，其特征在于，
在所述工序(a)中，通过交替地重复进行从倾斜方向对所述半导体晶片的表面照射第1原子的工序以及使所述半导体晶片相对于与其表面垂直的轴而逐个180°地旋转的工序，来将构成所述纳米弹簧层的所述弹簧做成锯齿形状。
CN201380069778.1A 2013-01-09 2013-01-09 半导体装置及其制造方法 Pending CN104903998A (zh)

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