JPS63292675A - プレ−ナ型サイリスタ - Google Patents

プレ−ナ型サイリスタ

Info

Publication number
JPS63292675A
JPS63292675A JP12890487A JP12890487A JPS63292675A JP S63292675 A JPS63292675 A JP S63292675A JP 12890487 A JP12890487 A JP 12890487A JP 12890487 A JP12890487 A JP 12890487A JP S63292675 A JPS63292675 A JP S63292675A
Authority
JP
Japan
Prior art keywords
layer
base layer
type
emitter
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12890487A
Other languages
English (en)
Inventor
Yoshio Okamura
岡村　良夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12890487A priority Critical patent/JPS63292675A/ja
Publication of JPS63292675A publication Critical patent/JPS63292675A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、すべてＰＮ接合端が表面に終端され、この接
合端が表面を覆う酸化膜で保護されたプレーナ型サイリ
スタ、特に高耐圧のプレーナ型サイリスタに関する。
〔従来の技術〕
従来のプレーナ型サイリスタを第２図の断面図に示す。
第２図において、高抵抗Ｎ型半導体基板１の下面全面Ｋ
Ｐエミッタ層３が形成され、さらに、Ｐ型不純物の突き
抜は拡散により、下面のＰエミッタ層３と連通している
外周側面部のＰエミッタ層３ａが形成されて、Ｎ型半導
体基板１０元来の高抵抗Ｎ型層はＰエミッタ層３，３ａ
に囲まれたＮベース層１を形成している。しかして、Ｎ
ベース層１内の表面側にＰベース層２が、また、Ｐペー
ス層２内の表面側ＫＮエミッタ層６が形成されて、全体
として、酸化膜７で表面接合端が保護されたＰＮＰＮ四
層構造のサイリスタが得られている。なお、Ｐベース層
２と外周のＰエミッタ層３との間にＮ＋チャンネルスト
ッパ４が設けられている。
〔発明が解決しようとする問題点〕
上述した従来型のプレーナ型サイリスタはブレークダウ
ン電圧が頭側において〜６００Ｖ、逆側において〜７０
０Ｖ程度である。本構造を高耐圧化する場合、頭側は接
合が浅い為高耐圧を得にくい。又、逆側はＰエミッタ層
３，３ａ及びＮエミッタ層６にわたり空乏層が拡がり、
表面の電界が強いため、外部イオンの影響を受けやすく
なり劣化するなどの欠点がある。
〔問題点を解決するための手段〕
本発明はかかる従来の欠点を解決するために、半導体素
子表面近傍の電界強度を弱める構造とし、接合の降伏が
界面より遠い場所でおこるようにし、耐圧の安定性を得
るものである。すなわち、頭側にてはＰ型ベース層の曲
率を緩和する形でＰ形フローティングリング層を設ける
。又逆側では、突き抜は拡散の側面Ｐ型エミッタ層をそ
のままＰＮ接合耐圧として用い、Ｐ膨突き抜は拡散した
窓より外側にＰ＋拡散層（Ｎ反転防止）を設けている。
〔実施例〕
つぎに本発明を実施例により説明する。
第１図は本発明の一実施例の断面図である。第１図にお
いて、底面および側面のＰエミッタ層３゜３ａ１その内
側の高比抵抗Ｎペース層１、さらにその内部のＰベース
層２、またさらにその内部のＮエミッタ層６のＰＮＰＮ
の四層構造のプレーナ型サイリスタであり、また、Ｓ　
ｉ　０２膜７で覆われたＮベース層１の表面側にＰペー
ス層２を囲むようなＰ型フローティングリング５が設け
られている。しかして、Ｎベース層１の不純物濃度は〜
１×ＩＱ１４ｃｍ３．Ｐベース層２及びＰ形フローティ
ングリング層５の表面濃度は〜Ｉ　Ｘ　１０１８ｃｍ−
３であり、拡散深さは４０〜４７μｍである。また、Ｐ
エミッタＪ＠３ａの表面側では、Ｐベース層２の濃度以
下の表面濃度を有するが、その外周縁端部には戸反転防
止層９が設けられている。下面側ではＰベース層２と同
等の表面濃度である。Ｐ形エミッタ層側面部３ａはＮ形
高抵抗層１を突き抜ける形で設けられている。
本実施例においては表面部の順方向耐圧を有する接合を
、Ｐペース層２．Ｎ型高抵抗層１．Ｐ型フローティング
層５．Ｎ形高抵抗層１０４層にて形成している。又逆方
向耐圧は、Ｐ形エミッタ層３ａ及びＮ形高抵抗層ｌ及び
反転防止の為にＰ形エミッタ層の拡散窓より外側より拡
散したＰ　層／８を反転防止として用いる事で達成して
いる。
〔発明の効果〕
本発明は、型側耐圧をフローティングリング構造により
Ｐペース層の曲率による耐圧低下を防ぐことが可能とな
ると共に、逆側耐圧については、Ｐエミッタ層の不純物
濃度が低いことによる＝ｎ外部イオンによる影響をＰ形
反転防止層により最小にすることが出来る。よって、接
合の降伏はより界面より遠い場所で起こる様になり、逆
バイアス印加時の可動イオンの影響を受けにくくなり、
耐圧の安定性が改善される。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図、第２図は従来のプ
レーナ型サイリスタの断面図である。 １・・・・・・Ｎ型基板（Ｎペース層）、２・・・・・
・Ｐベース層、３・・・・・・Ｐエミッタ層、３ａ・・
・・・・側面Ｐエミッタ層、４・・・・・・Ｎチャンネ
ルストッパ、５・・・・・・Ｐ減フローティングリング
、６・・・・・・Ｎエミッタ層、７・・・・・・酸化膜
、８・・・・・・Ｐ反転防止層。 ／　　：　Ｎへ゛−スノー ど　　：　　ｒ’＜’−Ｘノｉ ３　　二　βエミ、７りＡ酉 ３ａ　　：　　イ日りｉ　βエミッタ屑４　　：　／ｖ
＋ザセ、ンネノｔ、、ｔトゾＹ汐　：　フローカシグカ
／グ 乙　　　：　　Ｎエミミゾタ層 Ｚ　　：　　淫乏北Ｈシ町 ８　　：　ｒノえ転ｖｊ、ｌＪ

Claims (1)

    【特許請求の範囲】
  1. 高比抵抗Ｎベース層と、このＮベース層の底面と外周側
    面に形成されたＰエミッタ層と、前記Ｎベース層内の表
    面側に選択的に形成されたＰベース層と、このＰベース
    層内の表面側に選択的に形成されたＮエミッタ層とを有
    するプレーナ型サイリスタにおいて、前記Ｎベース層内
    の表面側に、前記Ｐベース層を囲むように形成されたＰ
    型フローティングリングと、このフローティングリング
    の外側に形成されたＮ＾＋型チャンネルストッパと、前
    記側面Ｐベース層表面側外周部に形成されたＰ＾＋型反
    転防止層とを有することを特徴とするプレーナ型サイリ
    スタ。
JP12890487A 1987-05-25 1987-05-25 プレ−ナ型サイリスタ Pending JPS63292675A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12890487A JPS63292675A (ja) 1987-05-25 1987-05-25 プレ−ナ型サイリスタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12890487A JPS63292675A (ja) 1987-05-25 1987-05-25 プレ−ナ型サイリスタ

Publications (1)

Publication Number Publication Date
JPS63292675A true JPS63292675A (ja) 1988-11-29

Family

ID=14996235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12890487A Pending JPS63292675A (ja) 1987-05-25 1987-05-25 プレ−ナ型サイリスタ

Country Status (1)

Country Link
JP (1) JPS63292675A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6773968B1 (en) * 1998-05-13 2004-08-10 Micron Technology, Inc. High density planar SRAM cell using bipolar latch-up and gated diode breakdown

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55133569A (en) * 1979-04-06 1980-10-17 Hitachi Ltd Semiconductor device
JPS5628777U (ja) * 1979-08-09 1981-03-18
JPS5778171A (en) * 1980-11-04 1982-05-15 Hitachi Ltd Thyristor
JPS6251764B2 (ja) * 1981-09-04 1987-11-02 Kubota Ltd

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55133569A (en) * 1979-04-06 1980-10-17 Hitachi Ltd Semiconductor device
JPS5628777U (ja) * 1979-08-09 1981-03-18
JPS5778171A (en) * 1980-11-04 1982-05-15 Hitachi Ltd Thyristor
JPS6251764B2 (ja) * 1981-09-04 1987-11-02 Kubota Ltd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6773968B1 (en) * 1998-05-13 2004-08-10 Micron Technology, Inc. High density planar SRAM cell using bipolar latch-up and gated diode breakdown

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