JPS63124133A - 全加算回路 - Google Patents

全加算回路

Info

Publication number
JPS63124133A
JPS63124133A JP61270693A JP27069386A JPS63124133A JP S63124133 A JPS63124133 A JP S63124133A JP 61270693 A JP61270693 A JP 61270693A JP 27069386 A JP27069386 A JP 27069386A JP S63124133 A JPS63124133 A JP S63124133A
Authority
JP
Japan
Prior art keywords
signal
exclusive
circuit
carry
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61270693A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0450613B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Ikuo Yasui
安井　郁夫
Yukihiko Shimazu
之彦 島津
Tooru Kengaku
見学　徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61270693A priority Critical patent/JPS63124133A/ja
Priority to US07/113,612 priority patent/US4870609A/en
Publication of JPS63124133A publication Critical patent/JPS63124133A/ja
Publication of JPH0450613B2 publication Critical patent/JPH0450613B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
JP61270693A 1986-11-13 1986-11-13 全加算回路 Granted JPS63124133A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61270693A JPS63124133A (ja) 1986-11-13 1986-11-13 全加算回路
US07/113,612 US4870609A (en) 1986-11-13 1987-10-26 High speed full adder using complementary input-output signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61270693A JPS63124133A (ja) 1986-11-13 1986-11-13 全加算回路

Publications (2)

Publication Number Publication Date
JPS63124133A true JPS63124133A (ja) 1988-05-27
JPH0450613B2 JPH0450613B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-08-14

Family

ID=17489640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61270693A Granted JPS63124133A (ja) 1986-11-13 1986-11-13 全加算回路

Country Status (2)

Country Link
US (1) US4870609A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS63124133A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04114211A (ja) * 1990-09-04 1992-04-15 Daifuku Co Ltd 移動車の走行制御装置
JPH04283829A (ja) * 1991-03-13 1992-10-08 Nec Corp 全加算器
JPH07200257A (ja) * 1993-12-28 1995-08-04 Nec Corp Ｎｍｏｓパストランジスタ回路と加算器

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148387A (en) * 1989-02-22 1992-09-15 Hitachi, Ltd. Logic circuit and data processing apparatus using the same
JP2540934B2 (ja) * 1989-03-09 1996-10-09 三菱電機株式会社 論理回路装置
US5121352A (en) * 1990-02-06 1992-06-09 Micron Technology, Inc. Multiplier-accumulator circuit array operable in multiple modes
WO1991013392A2 (en) * 1990-02-12 1991-09-05 Micron Technology, Inc. Easily configurable fully differential fast logic circuit
US5162796A (en) * 1990-07-31 1992-11-10 Inmos Limited Digital signal inversion employing cross-over switch
US5491429A (en) * 1994-09-16 1996-02-13 At&T Global Information Solutions Company Apparatus for reducing current consumption in a CMOS inverter circuit
US5636157A (en) * 1994-10-03 1997-06-03 International Business Machines Corporation Modular 64-bit integer adder
US5875124A (en) * 1995-02-22 1999-02-23 Texas Instruments Japan Ltd. Full adder circuit
US6356112B1 (en) 2000-03-28 2002-03-12 Translogic Technology, Inc. Exclusive or/nor circuit
US7260595B2 (en) * 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
US7170317B2 (en) * 2003-05-23 2007-01-30 Arithmatica Limited Sum bit generation circuit
US8135768B2 (en) * 2005-03-02 2012-03-13 Mtekvision Co., Ltd. Adder with reduced capacitance
US10672756B2 (en) * 2018-11-05 2020-06-02 Samsung Electronics Co., Ltd. Area and power efficient circuits for high-density standard cell libraries

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59139447A (ja) * 1983-01-28 1984-08-10 Matsushita Electric Ind Co Ltd 全加算器
US4689763A (en) * 1985-01-04 1987-08-25 Advanced Micro Devices, Inc. CMOS full adder circuit
US4709346A (en) * 1985-04-01 1987-11-24 Raytheon Company CMOS subtractor
US4713790A (en) * 1985-07-31 1987-12-15 Motorola, Inc. Exclusive OR/NOR gate having cross-coupled transistors
JPH06170636A (ja) * 1992-10-15 1994-06-21 Osamu Fukushima パイプ切断装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04114211A (ja) * 1990-09-04 1992-04-15 Daifuku Co Ltd 移動車の走行制御装置
JPH04283829A (ja) * 1991-03-13 1992-10-08 Nec Corp 全加算器
JPH07200257A (ja) * 1993-12-28 1995-08-04 Nec Corp Ｎｍｏｓパストランジスタ回路と加算器

Also Published As

Publication number Publication date
JPH0450613B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-08-14
US4870609A (en) 1989-09-26

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