JPS6194349A - 樹脂封止形半導体装置の製造方法及びその製造方法に使用するリ−ドフレ−ム - Google Patents

樹脂封止形半導体装置の製造方法及びその製造方法に使用するリ−ドフレ−ム

Info

Publication number
JPS6194349A
JPS6194349A JP59215235A JP21523584A JPS6194349A JP S6194349 A JPS6194349 A JP S6194349A JP 59215235 A JP59215235 A JP 59215235A JP 21523584 A JP21523584 A JP 21523584A JP S6194349 A JPS6194349 A JP S6194349A
Authority
JP
Japan
Prior art keywords
strip
lead frame
resin
strips
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59215235A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0472389B2 (enExample
Inventor
Sadao Yoshida
吉田　定雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP59215235A priority Critical patent/JPS6194349A/ja
Publication of JPS6194349A publication Critical patent/JPS6194349A/ja
Publication of JPH0472389B2 publication Critical patent/JPH0472389B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP59215235A 1984-10-16 1984-10-16 樹脂封止形半導体装置の製造方法及びその製造方法に使用するリ−ドフレ−ム Granted JPS6194349A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59215235A JPS6194349A (ja) 1984-10-16 1984-10-16 樹脂封止形半導体装置の製造方法及びその製造方法に使用するリ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59215235A JPS6194349A (ja) 1984-10-16 1984-10-16 樹脂封止形半導体装置の製造方法及びその製造方法に使用するリ−ドフレ−ム

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP1150427A Division JPH0736430B2 (ja) 1989-06-15 1989-06-15 樹脂封止形半導体装置の製造方法
JP1150428A Division JPH06103728B2 (ja) 1989-06-15 1989-06-15 樹脂封止形半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6194349A true JPS6194349A (ja) 1986-05-13
JPH0472389B2 JPH0472389B2 (enExample) 1992-11-18

Family

ID=16668951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59215235A Granted JPS6194349A (ja) 1984-10-16 1984-10-16 樹脂封止形半導体装置の製造方法及びその製造方法に使用するリ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS6194349A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0242751A (ja) * 1989-06-15 1990-02-13 Sanken Electric Co Ltd 樹脂封止形半導体装置の製造方法
US5410804A (en) * 1991-03-15 1995-05-02 Asm-Fico Tooling B.V. Method for manufacturing a single product from integrated circuits received on a lead frame

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178352A (en) * 1981-04-28 1982-11-02 Matsushita Electronics Corp Manufacture of resin sealing type semiconductor device and lead frame employed thereon

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178352A (en) * 1981-04-28 1982-11-02 Matsushita Electronics Corp Manufacture of resin sealing type semiconductor device and lead frame employed thereon

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0242751A (ja) * 1989-06-15 1990-02-13 Sanken Electric Co Ltd 樹脂封止形半導体装置の製造方法
US5410804A (en) * 1991-03-15 1995-05-02 Asm-Fico Tooling B.V. Method for manufacturing a single product from integrated circuits received on a lead frame

Also Published As

Publication number Publication date
JPH0472389B2 (enExample) 1992-11-18

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