JPS5940397A - デ−タ読み出し回路 - Google Patents

デ−タ読み出し回路

Info

Publication number
JPS5940397A
JPS5940397A JP57150902A JP15090282A JPS5940397A JP S5940397 A JPS5940397 A JP S5940397A JP 57150902 A JP57150902 A JP 57150902A JP 15090282 A JP15090282 A JP 15090282A JP S5940397 A JPS5940397 A JP S5940397A
Authority
JP
Japan
Prior art keywords
transistor
level
data
output
output line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57150902A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0344400B2 (en, 2012
Inventor
Hiroaki Suzuki
宏明 鈴木
Itsuo Sasaki
逸夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57150902A priority Critical patent/JPS5940397A/ja
Priority to DE8383106973T priority patent/DE3378238D1/de
Priority to EP83106973A priority patent/EP0105105B1/en
Priority to US06/518,348 priority patent/US4592021A/en
Publication of JPS5940397A publication Critical patent/JPS5940397A/ja
Publication of JPH0344400B2 publication Critical patent/JPH0344400B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
JP57150902A 1982-08-31 1982-08-31 デ−タ読み出し回路 Granted JPS5940397A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57150902A JPS5940397A (ja) 1982-08-31 1982-08-31 デ−タ読み出し回路
DE8383106973T DE3378238D1 (de) 1982-08-31 1983-07-15 Data readout circuit for a mos transistor array
EP83106973A EP0105105B1 (en) 1982-08-31 1983-07-15 Data readout circuit for a mos transistor array
US06/518,348 US4592021A (en) 1982-08-31 1983-07-29 Data readout circuit for an MOS transistor array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57150902A JPS5940397A (ja) 1982-08-31 1982-08-31 デ−タ読み出し回路

Publications (2)

Publication Number Publication Date
JPS5940397A true JPS5940397A (ja) 1984-03-06
JPH0344400B2 JPH0344400B2 (en, 2012) 1991-07-05

Family

ID=15506878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57150902A Granted JPS5940397A (ja) 1982-08-31 1982-08-31 デ−タ読み出し回路

Country Status (4)

Country Link
US (1) US4592021A (en, 2012)
EP (1) EP0105105B1 (en, 2012)
JP (1) JPS5940397A (en, 2012)
DE (1) DE3378238D1 (en, 2012)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4709352A (en) * 1984-11-19 1987-11-24 Oki Electric Industry Co., Ltd. MOS read-only memory systems
JPH0793009B2 (ja) * 1984-12-13 1995-10-09 株式会社東芝 半導体記憶装置
JPH0713878B2 (ja) * 1985-06-20 1995-02-15 三菱電機株式会社 Ｃｍｏｓトランジスタ回路
JPS63131568A (ja) * 1986-11-21 1988-06-03 Toshiba Corp 半導体メモリ装置
JP2617189B2 (ja) * 1987-08-03 1997-06-04 沖電気工業株式会社 電流検出回路
JPH0727718B2 (ja) * 1988-02-19 1995-03-29 日本電気株式会社 センス回路
JPH0817034B2 (ja) * 1988-10-24 1996-02-21 三菱電機株式会社 半導体記憶装置
FR2751778B1 (fr) * 1996-07-23 1998-11-06 Sgs Thomson Microelectronics Memoire accessible en lecture seulement
US5894432A (en) * 1997-07-08 1999-04-13 International Business Machines Corporation CMOS memory cell with improved read port
US6424571B1 (en) * 2001-05-01 2002-07-23 Micron Technology, Inc. Sense amplifier with data line precharge through a self-bias circuit and a precharge circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5634192A (en) * 1979-08-29 1981-04-06 Matsushita Electric Ind Co Ltd Memory unit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399736A (en) * 1977-02-10 1978-08-31 Toshiba Corp Semiconductor memory unit
EP0019987A1 (en) * 1979-06-01 1980-12-10 Motorola, Inc. High speed IGFET sense amplifier/latch
US4318014A (en) * 1979-07-27 1982-03-02 Motorola, Inc. Selective precharge circuit for read-only-memory
JPS5837636B2 (ja) * 1980-07-31 1983-08-17 富士通株式会社 半導体記憶装置
JPS57117188A (en) * 1981-01-12 1982-07-21 Toshiba Corp Sense amplifier circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5634192A (en) * 1979-08-29 1981-04-06 Matsushita Electric Ind Co Ltd Memory unit

Also Published As

Publication number Publication date
EP0105105B1 (en) 1988-10-12
US4592021A (en) 1986-05-27
EP0105105A2 (en) 1984-04-11
JPH0344400B2 (en, 2012) 1991-07-05
EP0105105A3 (en) 1986-11-05
DE3378238D1 (de) 1988-11-17

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