JPS5933553U - プロセツサ - Google Patents

プロセツサ

Info

Publication number
JPS5933553U
JPS5933553U JP1982135856U JP13585682U JPS5933553U JP S5933553 U JPS5933553 U JP S5933553U JP 1982135856 U JP1982135856 U JP 1982135856U JP 13585682 U JP13585682 U JP 13585682U JP S5933553 U JPS5933553 U JP S5933553U
Authority
JP
Japan
Prior art keywords
instruction
register
predetermined
control signals
control logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982135856U
Other languages
English (en)
Inventor
スタンレイ・エドワ−ド・グロ−ブス
Original Assignee
モトロ−ラ・インコ−ポレ−テツド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by モトロ−ラ・インコ−ポレ−テツド filed Critical モトロ−ラ・インコ−ポレ−テツド
Publication of JPS5933553U publication Critical patent/JPS5933553U/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は内部バス構成、プログラマブル・レジスタ及び
論理ブ冶ツクを備えた本考案の一実施例のブ遁ツク図、
第２図は第１図に示したブロック図の一部を詳細に図示
する論理図である。 １１・・・バス制御回路、１３・・・ホールト論理回路
、２１・・・タイミング論理回路、３５・・・再スター
ト論理回路、３６．　４０−・・インクレメント番レジ
スタ、４１・・・命令解読・制御回路、４３・・・レジ
スタ及びＡＬＵ制御線、４７・・・割込論理回路、５７
・・・双方性外部バス、５８．６６・・・プログラムカ
ウンタ、６５．６９・・・インデクスレジスタ、７０．
７６・・・スタックポインタ、８５・・・状態コード・
レジスタ、１００・・・命令セット指標レジスタ。　。

Claims (2)

    【実用新案登録請求の範囲】
  1. （１）複数の命令セットのうちの１つからの選択された
    実行命令を記憶する命令レジスタとそこに印加される１
    組の制御信号に応答してプロセッサの動作を制御する制
    御論理とを具えるプロセッサにおいて、命令が選択され
    た複数命令セットのうちの１つを指示する選択された命
    令セットを記憶する命令セット指標レジスタ、前記命令
    レジスタに結合され、そこに記憶された前記選択命令に
    応答する第１組の入力、前記命令セット指標レジスタに
    結合され、そこに記憶される前記命令セット指標レジス
    タに応答する第２組の入力、及び前記制御論理に結合さ
    れ、前記制御信号のセットをそこに印加する１組の出力
    、を有する命令解読論理列、を具備し、前記命令解読論
    理列は、前記命令セット指標レジスタが前記複数の命令
    セットのうちの所定の第１組（セット）から選択された
    第１命令を指示する命令セットを記憶する場合に、所定
    の第１ビツトパターンを有する第１命令を記憶する前記
    命令レジスタに応答して前記第１組の制御信号を前記制
    御論理に印加し、前記命令セット指標レジスタが前記複
    数の命令セットのうちの所定の第２組（セット）から選
    択された第２命令を指示する命令セットを記憶する場合
    に、所定の第１ビツトパターンとは異なる所定の第２ビ
    ツトパターンを有する第２命令を記憶する前記命令レジ
    スタに応答して同一の第１組の制御信号を前記制御論理
    に印加することを特徴とするプロセッサ。
  2. （２）前記命令解読論理列は、前記命令セット指標レジ
    スタが前記複数の命令セットのうちの所定の第２組（セ
    ット）から選択された第３命令を指示する命令セットを
    記憶する場合に、所定の一−−−前記第１ビットパター
    ンを有する第３命令を記憶する前記命令レジスタに応答
    して、前記第１組の制御信号とは異なる制御信号の第２
    組を前記制御論理に印加する前記特許請求の範囲第１項
    記載のプロセッサ。
JP1982135856U 1978-03-13 1982-09-07 プロセツサ Pending JPS5933553U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US885709 1978-03-13
US05/885,709 US4236204A (en) 1978-03-13 1978-03-13 Instruction set modifier register

Publications (1)

Publication Number Publication Date
JPS5933553U true JPS5933553U (ja) 1984-03-01

Family

ID=25387529

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2724379A Pending JPS54127243A (en) 1978-03-13 1979-03-08 Instruction set index register
JP1982135856U Pending JPS5933553U (ja) 1978-03-13 1982-09-07 プロセツサ

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2724379A Pending JPS54127243A (en) 1978-03-13 1979-03-08 Instruction set index register

Country Status (8)

Country Link
US (1) US4236204A (ja)
JP (2) JPS54127243A (ja)
DE (1) DE2907181C2 (ja)
FR (1) FR2420169B1 (ja)
GB (1) GB2016755B (ja)
HK (1) HK66884A (ja)
MY (1) MY8500495A (ja)
SG (1) SG18684G (ja)

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US5179703A (en) * 1987-11-17 1993-01-12 International Business Machines Corporation Dynamically adaptive environment for computer programs
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EP0344951A3 (en) * 1988-05-31 1991-09-18 Raytheon Company Method and apparatus for controlling execution speed of computer processor
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Also Published As

Publication number Publication date
GB2016755B (en) 1982-04-28
GB2016755A (en) 1979-09-26
HK66884A (en) 1984-08-31
FR2420169B1 (fr) 1986-08-22
DE2907181C2 (de) 1986-01-16
DE2907181A1 (de) 1979-09-20
SG18684G (en) 1985-02-15
MY8500495A (en) 1985-12-31
US4236204A (en) 1980-11-25
FR2420169A1 (fr) 1979-10-12
JPS54127243A (en) 1979-10-03

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