FR2420169A1 - Registre modificateur d'instructions - Google Patents

Registre modificateur d'instructions

Info

Publication number
FR2420169A1
FR2420169A1 FR7902571A FR7902571A FR2420169A1 FR 2420169 A1 FR2420169 A1 FR 2420169A1 FR 7902571 A FR7902571 A FR 7902571A FR 7902571 A FR7902571 A FR 7902571A FR 2420169 A1 FR2420169 A1 FR 2420169A1
Authority
FR
France
Prior art keywords
instruction
register
modifier register
modifier
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7902571A
Other languages
English (en)
Other versions
FR2420169B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of FR2420169A1 publication Critical patent/FR2420169A1/fr
Application granted granted Critical
Publication of FR2420169B1 publication Critical patent/FR2420169B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

a. Registre modificateur d'instructions. b. Registre caractérisé en ce qu'il comporte plusieurs états correspondant chacun à un jeu d'instructions, le circuit de commande et le décodage d'instructions coopérant avec ce registre modificateur pour activer celles des lignes de commande qui correspondent à l'un des mots d'instruction d'un jeu d'instructions pour représenter une instruction commune à ces jeux, en état stockée dans le registre d'instructions à condition que l'état du registre modificateur corresponde au jeu d'instructions contenant ce mot d'instruction.
FR7902571A 1978-03-13 1979-01-31 Registre modificateur d'instructions Expired FR2420169B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/885,709 US4236204A (en) 1978-03-13 1978-03-13 Instruction set modifier register

Publications (2)

Publication Number Publication Date
FR2420169A1 true FR2420169A1 (fr) 1979-10-12
FR2420169B1 FR2420169B1 (fr) 1986-08-22

Family

ID=25387529

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7902571A Expired FR2420169B1 (fr) 1978-03-13 1979-01-31 Registre modificateur d'instructions

Country Status (8)

Country Link
US (1) US4236204A (fr)
JP (2) JPS54127243A (fr)
DE (1) DE2907181C2 (fr)
FR (1) FR2420169B1 (fr)
GB (1) GB2016755B (fr)
HK (1) HK66884A (fr)
MY (1) MY8500495A (fr)
SG (1) SG18684G (fr)

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US4575797A (en) * 1981-05-22 1986-03-11 Data General Corporation Digital data processing system incorporating object-based addressing and capable of executing instructions belonging to several instruction sets
JPS5938870A (ja) * 1982-08-30 1984-03-02 Sharp Corp 電子式計算機
US4876639A (en) * 1983-09-20 1989-10-24 Mensch Jr William D Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit
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JPS6133546A (ja) * 1984-07-25 1986-02-17 Nec Corp 情報処理装置
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US5084814A (en) * 1987-10-30 1992-01-28 Motorola, Inc. Data processor with development support features
US5179703A (en) * 1987-11-17 1993-01-12 International Business Machines Corporation Dynamically adaptive environment for computer programs
NL8800071A (nl) * 1988-01-13 1989-08-01 Philips Nv Dataprocessorsysteem en videoprocessorsysteem, voorzien van een dergelijk dataprocessorsysteem.
EP0344951A3 (fr) * 1988-05-31 1991-09-18 Raytheon Company Méthode et dispositif pour régler la vitesse d'exécution d'une unité de traitement de données dans un ordinateur
US5280620A (en) * 1988-12-16 1994-01-18 U.S. Philips Corporation Coupling network for a data processor, including a series connection of a cross-bar switch and an array of silos
GB2266606B (en) * 1992-04-27 1996-02-14 Intel Corp A microprocessor with an external command mode
FR2693571B1 (fr) * 1992-07-13 1994-09-30 Texas Instruments France Système de traitement de données dont le programme de commande comporte des instructions dépendant de paramètres d'état.
JPH08509080A (ja) * 1992-07-13 1996-09-24 テキサス インスツルメンツ インコーポレイテッド プログラムループ処理のためのデバイスを備えたデータ処理システム
US5848289A (en) * 1992-11-27 1998-12-08 Motorola, Inc. Extensible central processing unit
GB2289353B (en) * 1994-05-03 1997-08-27 Advanced Risc Mach Ltd Data processing with multiple instruction sets
GB2307072B (en) * 1994-06-10 1998-05-13 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
US5649179A (en) * 1995-05-19 1997-07-15 Motorola, Inc. Dynamic instruction allocation for a SIMD processor
EP0790551A1 (fr) * 1996-02-16 1997-08-20 Koninklijke KPN N.V. Méthode pour modifier le jeu d'instruction d'une carte à puce
US5867681A (en) * 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
EP0858167A1 (fr) 1997-01-29 1998-08-12 Hewlett-Packard Company Processeur à réseau de portes programmables
EP0858168A1 (fr) 1997-01-29 1998-08-12 Hewlett-Packard Company Matrice de processeur à réseau de portes programmables
US5925124A (en) * 1997-02-27 1999-07-20 International Business Machines Corporation Dynamic conversion between different instruction codes by recombination of instruction elements
JP3340343B2 (ja) * 1997-03-13 2002-11-05 株式会社東芝 プロセッサ及び情報処理装置
US6076156A (en) * 1997-07-17 2000-06-13 Advanced Micro Devices, Inc. Instruction redefinition using model specific registers
US6000029A (en) 1997-11-03 1999-12-07 Motorola, Inc. Method and apparatus for affecting subsequent instruction processing in a data processor
DE69834942T2 (de) 1997-12-17 2007-06-06 Panasonic Europe Ltd., Uxbridge Vorrichtung zum Multiplizieren
DE69827589T2 (de) 1997-12-17 2005-11-03 Elixent Ltd. Konfigurierbare Verarbeitungsanordnung und Verfahren zur Benutzung dieser Anordnung, um eine Zentraleinheit aufzubauen
EP0924602B1 (fr) * 1997-12-17 2009-10-28 Panasonic Corporation Masquage d' instructions pour fournir des flots d'instructions à un processeur
DE69841256D1 (de) 1997-12-17 2009-12-10 Panasonic Corp Befehlsmaskierung um Befehlsströme einem Prozessor zuzuleiten
US6332215B1 (en) * 1998-12-08 2001-12-18 Nazomi Communications, Inc. Java virtual machine hardware for RISC and CISC processors
US20050149694A1 (en) * 1998-12-08 2005-07-07 Mukesh Patel Java hardware accelerator using microcode engine
US7225436B1 (en) 1998-12-08 2007-05-29 Nazomi Communications Inc. Java hardware accelerator using microcode engine
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
GB2367654B (en) 2000-10-05 2004-10-27 Advanced Risc Mach Ltd Storing stack operands in registers
GB2367653B (en) 2000-10-05 2004-10-20 Advanced Risc Mach Ltd Restarting translated instructions
US20020069402A1 (en) * 2000-10-05 2002-06-06 Nevill Edward Colles Scheduling control within a system having mixed hardware and software based instruction execution
EP1197847A3 (fr) * 2000-10-10 2003-05-21 Nazomi Communications Inc. Accélérateur Java en hardware avec machine à microcode
GB2369464B (en) 2000-11-27 2005-01-05 Advanced Risc Mach Ltd A data processing apparatus and method for saving return state
US7076771B2 (en) 2000-12-01 2006-07-11 Arm Limited Instruction interpretation within a data processing system
US7711926B2 (en) 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
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US3422404A (en) * 1966-02-23 1969-01-14 David E Ferguson Apparatus and method for decoding operation codes in digital computers

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FR2253435A5 (fr) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
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US3422404A (en) * 1966-02-23 1969-01-14 David E Ferguson Apparatus and method for decoding operation codes in digital computers

Non-Patent Citations (3)

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EXBK/74 *
EXBK/75 *

Also Published As

Publication number Publication date
GB2016755A (en) 1979-09-26
JPS54127243A (en) 1979-10-03
DE2907181C2 (de) 1986-01-16
DE2907181A1 (de) 1979-09-20
JPS5933553U (ja) 1984-03-01
FR2420169B1 (fr) 1986-08-22
US4236204A (en) 1980-11-25
MY8500495A (en) 1985-12-31
GB2016755B (en) 1982-04-28
HK66884A (en) 1984-08-31
SG18684G (en) 1985-02-15

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