KR830006739A - 데이터 처리장치 - Google Patents
데이터 처리장치 Download PDFInfo
- Publication number
- KR830006739A KR830006739A KR1019810002548A KR810002548A KR830006739A KR 830006739 A KR830006739 A KR 830006739A KR 1019810002548 A KR1019810002548 A KR 1019810002548A KR 810002548 A KR810002548 A KR 810002548A KR 830006739 A KR830006739 A KR 830006739A
- Authority
- KR
- South Korea
- Prior art keywords
- operands
- bytes
- calculator
- input
- data processing
- Prior art date
Links
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 2
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49936—Normalisation mentioned as feature only
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 가변연산수 길이명령의 일례를 나타낸 도면.
제2도 및 제3도는 제1도의 명령을 꺼번에 복수바이트 처리하는 종래예를 설명하기 위한 도면.
제4도 및 제5도는 본원 발명의 개요를 설명하기 위한 도면.
제6도 내지 제11도는 본원 발명의 일실시예를 나타낸 논리회로도.
제12도는 제8도의 데코오더의 입출력관계를 나타낸 도면.
Claims (2)
- 도면에 표시하고 본문에 상술한 바와 같이 기억장치상의 임의의 어드레스에서 시작되며, 임의의 바이트수의 길이를 갖는 제1 및 제2연산수를 처리하는 처리장치에 있어서, 복수바이트폭의 입력을 가지며 복수바이트의 제1 및 제2연산수를 동시에 연산 가능한 연산기와, 입력의 복수바이트내에서 연산수가 시작되는 어드레스와 연산수의 길이에서 연산기에 입력되는 데이터중, 연산에 불필요한 부분을 검출하는 제어회로와, 상기 제어회로의 제어를 받아서 상기 연산기에 입력되는 데이터중 연산에 불필요한 부분을 억지해서 제로 또는 1보증하기 위한게이트회로군(群)을가지며, 제2연산수 위치를 제1연산수 위치에 정합해서 연산하는 것을 특징으로 하는 데이터 처리장치.
- 상기 게이트회로군은 제1 및 제2연산수를 가산처리할 때는 연산기에 입력되는 데이터의 제1 및 제2연산수와도 연산에 불필요한 부분을 제로 보증하고, 제1 및 제2 연산수를 감산처리할때는 제1연산수의 불필요한 부분에는 제로 보증하고, 제2연산수의 불필요한 부분에는 1보증하는 것을 특징으로 하는 특허청구의 범위 1기재의 데이터 처리장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55118218A JPS5743239A (en) | 1980-08-27 | 1980-08-27 | Data processor |
JP80-118,218 | 1980-08-27 | ||
JP118218 | 1980-08-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR830006739A true KR830006739A (ko) | 1983-10-06 |
KR860000791B1 KR860000791B1 (ko) | 1986-06-25 |
Family
ID=14731136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019810002548A KR860000791B1 (ko) | 1980-08-27 | 1981-07-14 | 데이터처리장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US4456955A (ko) |
JP (1) | JPS5743239A (ko) |
KR (1) | KR860000791B1 (ko) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0827716B2 (ja) * | 1985-10-25 | 1996-03-21 | 株式会社日立製作所 | データ処理装置及びデータ処理方法 |
JP2504847B2 (ja) * | 1989-10-27 | 1996-06-05 | 甲府日本電気株式会社 | 10進デ―タのチェック回路 |
US5168571A (en) * | 1990-01-24 | 1992-12-01 | International Business Machines Corporation | System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data |
CA2045705A1 (en) * | 1990-06-29 | 1991-12-30 | Richard Lee Sites | In-register data manipulation in reduced instruction set processor |
JPH04116717A (ja) * | 1990-09-07 | 1992-04-17 | Koufu Nippon Denki Kk | オーバーフロー例外検出方式 |
US5438668A (en) | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
DE69329778T2 (de) | 1992-09-29 | 2001-04-26 | Seiko Epson Corp | System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor |
US6735685B1 (en) | 1992-09-29 | 2004-05-11 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
EP0593073A1 (en) * | 1992-10-16 | 1994-04-20 | Matsushita Electric Industrial Co., Ltd. | A processor incorporating shifters |
US5463746A (en) * | 1992-10-30 | 1995-10-31 | International Business Machines Corp. | Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes |
US6219773B1 (en) * | 1993-10-18 | 2001-04-17 | Via-Cyrix, Inc. | System and method of retiring misaligned write operands from a write buffer |
US5740398A (en) * | 1993-10-18 | 1998-04-14 | Cyrix Corporation | Program order sequencing of data in a microprocessor with write buffer |
US5584009A (en) * | 1993-10-18 | 1996-12-10 | Cyrix Corporation | System and method of retiring store data from a write buffer |
US5615402A (en) * | 1993-10-18 | 1997-03-25 | Cyrix Corporation | Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch |
US5471598A (en) * | 1993-10-18 | 1995-11-28 | Cyrix Corporation | Data dependency detection and handling in a microprocessor with write buffer |
US5673216A (en) * | 1995-12-19 | 1997-09-30 | International Business Machines Corporation | Process and system for adding or subtracting symbols in any base without converting to a common base |
US6557096B1 (en) * | 1999-10-25 | 2003-04-29 | Intel Corporation | Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types |
US6732203B2 (en) * | 2000-01-31 | 2004-05-04 | Intel Corporation | Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus |
JP3845814B2 (ja) * | 2000-08-10 | 2006-11-15 | 株式会社テルミナス・テクノロジー | 連想メモリとその検索方法及びルータとネットワークシステム |
US7716267B2 (en) * | 2004-08-30 | 2010-05-11 | Casio Computer Co., Ltd. | Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium |
US10459731B2 (en) * | 2015-07-20 | 2019-10-29 | Qualcomm Incorporated | Sliding window operation |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4135242A (en) * | 1977-11-07 | 1979-01-16 | Ncr Corporation | Method and processor having bit-addressable scratch pad memory |
US4189768A (en) * | 1978-03-16 | 1980-02-19 | International Business Machines Corporation | Operand fetch control improvement |
US4219874A (en) * | 1978-03-17 | 1980-08-26 | Gusev Valery | Data processing device for variable length multibyte data fields |
US4268909A (en) * | 1979-01-02 | 1981-05-19 | Honeywell Information Systems Inc. | Numeric data fetch - alignment of data including scale factor difference |
JPS6041768B2 (ja) * | 1979-01-19 | 1985-09-18 | 株式会社日立製作所 | デ−タ処理装置 |
-
1980
- 1980-08-27 JP JP55118218A patent/JPS5743239A/ja active Granted
-
1981
- 1981-07-14 KR KR1019810002548A patent/KR860000791B1/ko active
- 1981-08-18 US US06/294,053 patent/US4456955A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS5743239A (en) | 1982-03-11 |
KR860000791B1 (ko) | 1986-06-25 |
US4456955A (en) | 1984-06-26 |
JPH028327B2 (ko) | 1990-02-23 |
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