JPS5848442A - 電子部品の封止方法 - Google Patents

電子部品の封止方法

Info

Publication number
JPS5848442A
JPS5848442A JP56147667A JP14766781A JPS5848442A JP S5848442 A JPS5848442 A JP S5848442A JP 56147667 A JP56147667 A JP 56147667A JP 14766781 A JP14766781 A JP 14766781A JP S5848442 A JPS5848442 A JP S5848442A
Authority
JP
Japan
Prior art keywords
frame
semiconductor element
resin
sealing
printing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56147667A
Other languages
English (en)
Inventor
Kaoru Shimizu
薫 志水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56147667A priority Critical patent/JPS5848442A/ja
Publication of JPS5848442A publication Critical patent/JPS5848442A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は電子部品たとえば半導体素子の封止力２７−−
・　　　、− 法に関するものである。
ガラスエポキシ樹脂基板やセラミック基板あるいは金属
板の表面を樹脂コーティングしてなる回路用基板上に所
望のパターンの導体を形成し、これに直接半導体素子を
装着し、かつ半導体素子の外部接続用端子電極と上記導
体とを金（ムＵ）やアルミニウム（ムＥ）等の金属細線
で接続してなる半導体装置においては、半導体素子の封
止手段として樹脂ボッティング方法が一般的に用いられ
ている。
詳しくは、半導体素子および金属細線の外周部を包囲す
るように所定形状たとえば矩形の枠体を接着等の手段で
固定し、さらにこの枠内に液状の樹脂部材を充満させて
封止する方法である。
しかし上述の方法は、枠体を使用しているため封止構造
Ω小形化が限定されたり、あるいは枠体を接着しなけれ
ばならず、このため作業内容が煩わしく工数を要し、自
動化が困難であるといった問題を有している。
本発明は上記問題点を解決した電子部品の封止方法を提
供するもので、以下、本発明を半導体素子を封止する例
でもって図面を参照して説明する。
第１図、第２図および第３図は本発１１の第１の実施例
を説明するだめの要部断面図である。
まず、第１図に示すことく、表面に所望のパターンの導
体４を配設し；てなる回路用基板３上に。
半導体素子１を包囲するごとくリング状あるいは矩形等
の所望の枠形状に接着部材を印刷し、所定に硬化させて
印刷枠５を形成する。
第１図に示す実施例において、接着部材としては紫外線
硬化型樹脂を用い、枠寸法としては印１ｄｉ膜厚Ｈ＃　
３０　Ｑ　〜５００　ｐ　ｍ　、印刷幅ｗ＝ｓｏ。
〜８ｏｏμ毒とし、紫外線および加熱手段の併用により
硬化させた。　　　′ また、印刷手段としてはステンレスもしくは合成樹脂で
製版したスクリーン印刷の方法を用いたつスクリーン印
刷の場合、樹脂粘度は５００〜７００ＰＳ（室温２５°
Ｃ）とした。
第１図のごとく印刷枠５を所望範囲に基板３上に形成し
たのち、第２図に示すように、半導体装置に装着（グイ
ボンド）される。さらに半導体素子１の端子電極（図示
せず）と導体４とは金線６によって電気的導通状態に接
続（ワイヤボンド）される。
その後、半導体素子１および金線６を樹脂封止すべく所
定形状に成形した樹脂ペレットもしくは液状の樹脂部材
７たとえばエポキシ樹脂等を前記枠６内に所定量だけ注
入し、第３図に示すととく、枠６と樹脂部材了によって
半導体素子１および金線６を埋設するととく注型する。
注型後、樹脂部材７の硬化を所定温度で所定時間たとえ
ば１６００Ｃで４時間加熱することによシ半導体素子１
の封止が完了する。
第４図ならびに第６図は本発明の他の実施例を説明する
だめのもので、第４図の場合は凹部８を設けた基板３０
に凹部８を包囲するととく印刷手段を用いて印刷枠５ム
を形成し、凹部８内に装着した半導体素子１を樹脂封止
する様にしたもので。
印刷枠６ムの高さく印刷膜厚寸法Ｈ）寸法を第１図の場
合より低く形成し、封止寸法の薄形化を図った例である
。
第６図は半導体素子１を多数個同時に能率よく封止する
ようにしたもので、所定のパターンの導体（図示せず）
を所定ピッチ間隔ＣＰ）毎に多行多列に配設してなる回
路用基板１００に、リング状枠５Ｂを所定ピッチ間隔（
Ｐ）毎に所定に印刷して硬化させ、その後、各リング状
枠５Ｂ内に半導体素子１を装着し、“周知のワイヤボン
ドおよび樹脂注入硬化、特性検査等の工程を経て封止す
るようにしたものである。そして、樹脂封止後、二点鎖
線で′示す位置で、すなわちピッチ（Ｐ）毎に縦および
横方向に所定に切断することにより、所望の電子両路を
塔載してなる回路用基板（電子部品）を得ることが出来
る。
なお、上記実施例においては、印刷枠を形成する部材と
して紫外線硬化型の接着樹脂を印刷した例を述べたが、
枠部材としては紫外線硬化型樹脂に限定されるものでは
なく、熱硬化型樹脂等の任意の部材を用いてもよいこと
は言うまでもない。
さらに印刷する枠形状もリング状′、矩形状等、任意で
、必ずしも閉ループを形成する必要がなく、注型樹脂の
流れ防止に適したせき形状と寸法を選択すればよい。
上述のごとく本発明の封止方法は、注型樹脂部材の流れ
防止を印刷枠によって実施するようにしたもので、単体
部品としての枠体を使用したり枠体を接着する必要がな
いうえ、封止構造の小形化が図れ、さらには作業能率の
向上ならびに自動化を可能にする等、多くの効果を有す
るものである。
【図面の簡単な説明】
第１図は本発明の一実施例における回路用基板に印刷枠
を形成した状態の要部断面図、第２図は第１図において
半導体素子を装着しワイヤボンドした状態の要部断面図
、第３図は第２図において樹脂封止した状態の要部断面
図、第４図は本発明の池の実施°側番説明するための封
止後の半導体装置の要部断面図、第６図は本発明の更に
別の方施例を忌明するための封止過程の平面図である。 １・・・・・・半導体素子、３，３０’、１００・・・
・・・回路６・・・・・・金線、７・・・・・・樹脂部
材、８・・・・・・凹部。 代理人の氏名　弁理士　中　尾　赦　男　ほか１名第１
図 第２図 第３図 り 第４図 第５図 ／

Claims (1)

  1. 【特許請求の範囲】 （１）表面に所定のパターンの導体を配設してなる回路
    用基板上に印刷手段を用いて所定形状の印刷枠を形成し
    、所定に硬化させた後、前記印刷枠内に電子部品を装着
    し、前記電子部品の端子電極と前記導電とを導電部材で
    接続したのち、前記印刷枠内に注型樹脂部材を充填して
    硬化させることにより前記電子部品を封止するようにし
    たことを特徴とする電子部品の封止方法。 （２、特許請求の範囲第（１）項の記載において、前記
    印刷枠の印刷膜厚寸法を３００〜５００μｍとしたこと
    を特徴とする電子部品の封止方法。 （３）特許請求の範囲第０）項または第（２）項の記載
    において、印刷枠の部材を紫外線硬化型繭脂とし、　た
    ことを４徴とする電子部品の封止方法。
JP56147667A 1981-09-17 1981-09-17 電子部品の封止方法 Pending JPS5848442A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56147667A JPS5848442A (ja) 1981-09-17 1981-09-17 電子部品の封止方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56147667A JPS5848442A (ja) 1981-09-17 1981-09-17 電子部品の封止方法

Publications (1)

Publication Number Publication Date
JPS5848442A true JPS5848442A (ja) 1983-03-22

Family

ID=15435544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56147667A Pending JPS5848442A (ja) 1981-09-17 1981-09-17 電子部品の封止方法

Country Status (1)

Country Link
JP (1) JPS5848442A (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184834A (ja) * 1985-02-13 1986-08-18 Toshiba Chem Corp 樹脂封止型半導体装置の製造方法
JPS635644U (ja) * 1986-06-26 1988-01-14
US4860443A (en) * 1987-01-21 1989-08-29 Hughes Aircraft Company Method for connecting leadless chip package
JPH06169033A (ja) * 1992-11-30 1994-06-14 Nec Corp 半導体チップの実装方法
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6472598B1 (en) 1998-08-28 2002-10-29 Amkor Technology, Inc. Electromagnetic interference shield device with conductive encapsulant and dam
US6888259B2 (en) 2001-06-07 2005-05-03 Denso Corporation Potted hybrid integrated circuit
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53114068A (en) * 1977-03-15 1978-10-05 Tokyo Shibaura Electric Co Method of producing electronic part

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53114068A (en) * 1977-03-15 1978-10-05 Tokyo Shibaura Electric Co Method of producing electronic part

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184834A (ja) * 1985-02-13 1986-08-18 Toshiba Chem Corp 樹脂封止型半導体装置の製造方法
JPS635644U (ja) * 1986-06-26 1988-01-14
US4860443A (en) * 1987-01-21 1989-08-29 Hughes Aircraft Company Method for connecting leadless chip package
JPH06169033A (ja) * 1992-11-30 1994-06-14 Nec Corp 半導体チップの実装方法
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US6472598B1 (en) 1998-08-28 2002-10-29 Amkor Technology, Inc. Electromagnetic interference shield device with conductive encapsulant and dam
US6601293B1 (en) 1998-08-28 2003-08-05 Amkor Technology, Inc. Method of making an electromagnetic interference shield device
US6888259B2 (en) 2001-06-07 2005-05-03 Denso Corporation Potted hybrid integrated circuit

Similar Documents

Publication Publication Date Title
CN100390990C (zh) 堆叠多芯片封装和制造堆叠多芯片封装的方法
US7037756B1 (en) Stacked microelectronic devices and methods of fabricating same
US20060205117A1 (en) Solder masks used in encapsulation, assemblies including the solar mask, and methods
JPH05129473A (ja) 樹脂封止表面実装型半導体装置
US4054938A (en) Combined semiconductor device and printed circuit board assembly
US4766095A (en) Method of manufacturing eprom device
JPS5848442A (ja) 電子部品の封止方法
JPS58207645A (ja) 半導体装置
JPS6077446A (ja) 封止半導体装置
JP2006253315A (ja) 半導体装置
JP2003124401A (ja) モジュールおよびその製造方法
JPS5817646A (ja) 半導体装置の製造方法
JPS6175549A (ja) 半導体素子を含む電子回路及びその製造方法
JPS63310140A (ja) 電子回路装置とその製造方法
JP2902497B2 (ja) 混成集積回路基板の製造方法
JP3431993B2 (ja) Ｉｃパッケージの組立方法
JPS61216438A (ja) 封止された電子部品の製造方法
JP2555931B2 (ja) 半導体装置の製造方法
JPH01133328A (ja) 半導体素子の封止方法
JP2002368030A (ja) 樹脂封止型半導体装置及びその製造方法
JPH0521653A (ja) 樹脂封止型半導体装置
JPS59208769A (ja) 半導体装置
JPH04280459A (ja) 樹脂封止型半導体装置
JP2503053B2 (ja) Ｉｃモジュ―ルの製造方法
JPH0546270Y2 (ja)