JPS58123748A - 半導体装置用パツケ−ジ及びその製造方法 - Google Patents

半導体装置用パツケ−ジ及びその製造方法

Info

Publication number
JPS58123748A
JPS58123748A JP57234988A JP23498882A JPS58123748A JP S58123748 A JPS58123748 A JP S58123748A JP 57234988 A JP57234988 A JP 57234988A JP 23498882 A JP23498882 A JP 23498882A JP S58123748 A JPS58123748 A JP S58123748A
Authority
JP
Japan
Prior art keywords
lead
leads
semiconductor device
recess
central area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57234988A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0479141B2 (enExample
Inventor
アンソニ−・エル・アダムス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPS58123748A publication Critical patent/JPS58123748A/ja
Publication of JPH0479141B2 publication Critical patent/JPH0479141B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP57234988A 1982-01-11 1982-12-27 半導体装置用パツケ−ジ及びその製造方法 Granted JPS58123748A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US338754 1982-01-11
US06/338,754 US4514750A (en) 1982-01-11 1982-01-11 Integrated circuit package having interconnected leads adjacent the package ends

Publications (2)

Publication Number Publication Date
JPS58123748A true JPS58123748A (ja) 1983-07-23
JPH0479141B2 JPH0479141B2 (enExample) 1992-12-15

Family

ID=23326040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57234988A Granted JPS58123748A (ja) 1982-01-11 1982-12-27 半導体装置用パツケ−ジ及びその製造方法

Country Status (2)

Country Link
US (1) US4514750A (enExample)
JP (1) JPS58123748A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6049658A (ja) * 1983-08-29 1985-03-18 Nec Corp 半導体装置
JPS6189654A (ja) * 1984-10-04 1986-05-07 アマダ、エンジニアリング　アンド　サ−ビス　カンパニ−　インコ−ポレ−テツド デユアル・インライン・パツケ−ジ形半導体加工装置
JPS6329954U (enExample) * 1986-08-12 1988-02-27
JPH01108755A (ja) * 1987-10-21 1989-04-26 Toshiba Corp 半導体装置
JP4757495B2 (ja) * 2002-12-06 2011-08-24 クリー インコーポレイテッド 複合リードフレームｌｅｄパッケージおよびその製造方法

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680613A (en) * 1983-12-01 1987-07-14 Fairchild Semiconductor Corporation Low impedance package for integrated circuit die
JPS6132452A (ja) * 1984-07-25 1986-02-15 Hitachi Ltd リ−ドフレ−ムとそれを用いた電子装置
US4584627A (en) * 1985-01-09 1986-04-22 Rogers Corporation Flat decoupling capacitor and method of manufacture thereof
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US4829362A (en) * 1986-04-28 1989-05-09 Motorola, Inc. Lead frame with die bond flag for ceramic packages
JPH0815193B2 (ja) * 1986-08-12 1996-02-14 新光電気工業株式会社 半導体装置及びこれに用いるリードフレーム
JPH0719872B2 (ja) * 1987-03-30 1995-03-06 三菱電機株式会社 半導体装置
US4827376A (en) * 1987-10-05 1989-05-02 Olin Corporation Heat dissipating interconnect tape for use in tape automated bonding
US4849857A (en) * 1987-10-05 1989-07-18 Olin Corporation Heat dissipating interconnect tape for use in tape automated bonding
JP2708191B2 (ja) 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
US5466967A (en) * 1988-10-10 1995-11-14 Lsi Logic Products Gmbh Lead frame for a multiplicity of terminals
US5270570A (en) * 1988-10-10 1993-12-14 Lsi Logic Products Gmbh Lead frame for a multiplicity of terminals
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
US5233220A (en) * 1989-06-30 1993-08-03 Texas Instruments Incorporated Balanced capacitance lead frame for integrated circuits and integrated circuit device with separate conductive layer
DE68905475T2 (de) * 1989-07-18 1993-09-16 Ibm Halbleiter-speichermodul hoeher dichte.
US5256903A (en) * 1990-02-28 1993-10-26 Hitachi Ltd. Plastic encapsulated semiconductor device
JP2877479B2 (ja) * 1990-09-27 1999-03-31 株式会社東芝 半導体装置用リードフレーム
US5281849A (en) * 1991-05-07 1994-01-25 Singh Deo Narendra N Semiconductor package with segmented lead frame
JP2745933B2 (ja) * 1992-02-17 1998-04-28 日本電気株式会社 Ｔａｂ−集積回路
US5452511A (en) * 1993-11-04 1995-09-26 Chang; Alexander H. C. Composite lead frame manufacturing method
US5820014A (en) 1993-11-16 1998-10-13 Form Factor, Inc. Solder preforms
US7073254B2 (en) 1993-11-16 2006-07-11 Formfactor, Inc. Method for mounting a plurality of spring contact elements
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US6048744A (en) 1997-09-15 2000-04-11 Micron Technology, Inc. Integrated circuit package alignment feature
US6362426B1 (en) * 1998-01-09 2002-03-26 Micron Technology, Inc. Radiused leadframe
JP2001168225A (ja) * 1999-12-13 2001-06-22 Seiko Epson Corp 半導体チップのパッケージ
US6777786B2 (en) * 2001-03-12 2004-08-17 Fairchild Semiconductor Corporation Semiconductor device including stacked dies mounted on a leadframe
US6991960B2 (en) 2001-08-30 2006-01-31 Micron Technology, Inc. Method of semiconductor device package alignment and method of testing
US20070126445A1 (en) * 2005-11-30 2007-06-07 Micron Technology, Inc. Integrated circuit package testing devices and methods of making and using same
US9252782B2 (en) * 2011-02-14 2016-02-02 Qualcomm Incorporated Wireless chipset with a non-temperature compensated crystal reference
US11342276B2 (en) * 2019-05-24 2022-05-24 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing semiconductor device
JP2022542346A (ja) 2019-08-01 2022-10-03 インフィニット クーリング インコーポレイテッド 流体をガス流から収集するためのシステム及び方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617819A (en) * 1970-10-15 1971-11-02 Sylvania Electric Prod A semiconductor device having a connecting pad of low resistivity semiconductor material interconnecting gold electrodes and aluminum contacts of an enclosure
US3714370A (en) * 1972-01-24 1973-01-30 North American Rockwell Plastic package assembly for electronic circuit and process for producing the package
US4012768A (en) * 1975-02-03 1977-03-15 Motorola, Inc. Semiconductor package
US4141712A (en) * 1977-07-18 1979-02-27 Diacon Inc. Manufacturing process for package for electronic devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6049658A (ja) * 1983-08-29 1985-03-18 Nec Corp 半導体装置
JPS6189654A (ja) * 1984-10-04 1986-05-07 アマダ、エンジニアリング　アンド　サ−ビス　カンパニ−　インコ−ポレ−テツド デユアル・インライン・パツケ−ジ形半導体加工装置
JPS6329954U (enExample) * 1986-08-12 1988-02-27
JPH01108755A (ja) * 1987-10-21 1989-04-26 Toshiba Corp 半導体装置
JP4757495B2 (ja) * 2002-12-06 2011-08-24 クリー インコーポレイテッド 複合リードフレームｌｅｄパッケージおよびその製造方法

Also Published As

Publication number Publication date
US4514750A (en) 1985-04-30
JPH0479141B2 (enExample) 1992-12-15

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