JPS5586123A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5586123A
JPS5586123A JP16163978A JP16163978A JPS5586123A JP S5586123 A JPS5586123 A JP S5586123A JP 16163978 A JP16163978 A JP 16163978A JP 16163978 A JP16163978 A JP 16163978A JP S5586123 A JPS5586123 A JP S5586123A
Authority
JP
Japan
Prior art keywords
substrate
field
ultraviolet rays
semiconductor substrate
interface level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16163978A
Other languages
Japanese (ja)
Other versions
JPS6041849B2 (en
Inventor
Masanao Itoga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16163978A priority Critical patent/JPS6041849B2/en
Publication of JPS5586123A publication Critical patent/JPS5586123A/en
Publication of JPS6041849B2 publication Critical patent/JPS6041849B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce an interface level by placing a semiconductor substrate covered with an insulating film in a high frequency field, heating and irradiating ultraviolet rays thereto.
CONSTITUTION: A semiconductor substrate 1 is placed in a field about 13.56MHz, and ultraviolet rays and infrared rays 4 are irradiated to the substrate 1. A treatment in N2-H2 atmosphere with field intensity at about 10kV/mm and substrate temperature at 200W500°C to prevent pn-junction from breakdown is not to involve a damage by plasma, and an interface level can be reduced at normal temperature as compared with a conventional annealing.
COPYRIGHT: (C)1980,JPO&Japio
JP16163978A 1978-12-23 1978-12-23 Manufacturing method of semiconductor device Expired JPS6041849B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16163978A JPS6041849B2 (en) 1978-12-23 1978-12-23 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16163978A JPS6041849B2 (en) 1978-12-23 1978-12-23 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5586123A true JPS5586123A (en) 1980-06-28
JPS6041849B2 JPS6041849B2 (en) 1985-09-19

Family

ID=15739003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16163978A Expired JPS6041849B2 (en) 1978-12-23 1978-12-23 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6041849B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63138741A (en) * 1986-12-01 1988-06-10 Nippon Telegr & Teleph Corp <Ntt> Annealing device for compound semiconductor substrate
JPH07321061A (en) * 1994-10-03 1995-12-08 Sony Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63138741A (en) * 1986-12-01 1988-06-10 Nippon Telegr & Teleph Corp <Ntt> Annealing device for compound semiconductor substrate
JPH07321061A (en) * 1994-10-03 1995-12-08 Sony Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6041849B2 (en) 1985-09-19

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