JPS63138741A - Annealing device for compound semiconductor substrate - Google Patents
Annealing device for compound semiconductor substrateInfo
- Publication number
- JPS63138741A JPS63138741A JP28424586A JP28424586A JPS63138741A JP S63138741 A JPS63138741 A JP S63138741A JP 28424586 A JP28424586 A JP 28424586A JP 28424586 A JP28424586 A JP 28424586A JP S63138741 A JPS63138741 A JP S63138741A
- Authority
- JP
- Japan
- Prior art keywords
- annealing
- electric field
- substrate
- compound semiconductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000137 annealing Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 150000001875 compounds Chemical class 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000005684 electric field Effects 0.000 claims abstract description 44
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000003213 activating effect Effects 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract description 14
- 238000009826 distribution Methods 0.000 abstract description 8
- 239000000969 carrier Substances 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- -1 silicon (Si) Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、化合物半導体基板のアニール装置に係り、特
に、化合物半導体基板に注入されたｐ型あるいはｎ型不
純物をアニールにより活性化させてそれぞれｐ型あるい
はｎ型導電層を形成するアニール装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an annealing apparatus for compound semiconductor substrates, and in particular, it activates p-type or n-type impurities implanted into a compound semiconductor substrate by annealing, The present invention relates to an annealing apparatus for forming a p-type or n-type conductive layer.
ガリウム・砒素（Ｇ ａ Ａ ｓ ）などの化合物半導
体基板にイオン注入により不純物イオン、例えばシリコ
ン（Ｓｉ） 、を注入する場合、不純物イオンにより結
晶欠陥が誘起され、これらの結晶欠陥を回復させるため
、通常、概略温度８００℃、時間１０分程度の保護膜付
アニールが行われている。ここで、保護膜はアニール中
に基板原子の抜は出しを防止するために設けるものであ
り、通常、窒化シリコン（ＳｉＮｘ）や酸化シリコン（
Ｓｉｎ２）などが用いられている。なお、この種の技術
が記載されている公知文献として、生駒、他３名著″化
合物半導体（１）、（２）”、株式会社、工業調査会、
１９８４年発行、がある。When impurity ions, such as silicon (Si), are implanted into a compound semiconductor substrate such as gallium arsenic (GaAs), crystal defects are induced by the impurity ions, and in order to recover these crystal defects, Normally, protective film annealing is performed at a temperature of about 800° C. for about 10 minutes. Here, the protective film is provided to prevent the extraction of substrate atoms during annealing, and is usually made of silicon nitride (SiNx) or silicon oxide (
Sin2) etc. are used. In addition, known documents describing this type of technology include "Compound Semiconductors (1), (2)" by Ikoma et al., Kogyo Research Association Co., Ltd.,
Published in 1984.
前記した従来技術においては、アニール過程中に基板内
に空孔が発生し、これらの空孔が単体で、あるいはこれ
らと注入不純物が結合した欠陥として、あるいはこれら
と基板原子が結合した欠陥として、アクセプタやドナー
として作用するため。In the above-mentioned conventional technology, vacancies are generated in the substrate during the annealing process, and these vacancies are present as single defects, as defects in which these vacancies are combined with implanted impurities, or as defects in which these vacancies are combined with substrate atoms. To act as an acceptor or donor.
得られた注入層の電気的特性は、注入不純物で決定され
るものと異なった複雑な特性を示す、このため、界面近
傍の電荷分布が乱され、基板の電気的特性の劣化や特性
値のばらつきが生じるという問題点があった。The electrical properties of the obtained implanted layer exhibit complex properties different from those determined by the implanted impurities.As a result, the charge distribution near the interface is disturbed, leading to deterioration of the electrical properties of the substrate and changes in the characteristic values. There was a problem that variations occurred.
本発明の目的は、化合物半導体基板の保護膜付アニール
時または保護膜無しのアニール時に界面近傍でのキャリ
ア濃度を高めることにより、イオン注入層の電気的特性
の改善、特にキャリア分布を界面近傍に集中させ、浅い
キャリア分布を得ることのできる、化合物半導体基板の
アニール装置を提供することにある。The purpose of the present invention is to improve the electrical characteristics of an ion-implanted layer, especially to improve the carrier distribution near the interface, by increasing the carrier concentration near the interface when a compound semiconductor substrate is annealed with a protective film or without a protective film. An object of the present invention is to provide an annealing device for a compound semiconductor substrate that can concentrate carriers and obtain a shallow carrier distribution.
上記目的は、化合物半導体基板に注入されたｐ型あるい
はｎ型不純物をアニールにより活性化させてそれぞれｐ
型あるいはｎ型導電層を形成するアニール装置において
、上記基板をアニールするアニール炉と、このアニール
炉の内部あるいは外部に設置されて上記基板に垂直に電
界を印加する電界印加装置とを備えたアニール装置とす
ることにより、達成される。The above purpose is to activate p-type or n-type impurities implanted into a compound semiconductor substrate by annealing, and to
An annealing apparatus for forming a type or n-type conductive layer, comprising an annealing furnace for annealing the substrate, and an electric field application device installed inside or outside the annealing furnace and applying an electric field perpendicular to the substrate. This can be achieved by using a device.
化合物半導体基板としてＧａＡｓ基板を例にとり本発明
の詳細な説明する。アニール中に基板面に垂直方向に、
イオン注入された面から裏側の面に電界を印加すると、
基板界面に負に帯電した砒素イオンが移動しやすくなる
と同時に、ガリウム空孔も移動しやすくなる。ドナーで
ある注入イオン（例えばＳｉ”）が置換したガリウム空
孔の増加と。The present invention will be described in detail by taking a GaAs substrate as an example of a compound semiconductor substrate. perpendicular to the substrate surface during annealing.
When an electric field is applied from the ion-implanted side to the back side,
At the same time, negatively charged arsenic ions move more easily to the substrate interface, gallium vacancies also move more easily. Increase in gallium vacancies replaced by donor implanted ions (e.g. Si'').
アクセプタである注入イオンが置換した砒素空孔の減少
とが同時に誘起され、高濃度でかつ浅い導電層が実現で
きることになる。At the same time, a reduction in arsenic vacancies substituted by implanted ions, which are acceptors, is induced, making it possible to realize a highly concentrated and shallow conductive layer.
以下１図面により本発明の詳細な説明する。 The present invention will be explained in detail below with reference to one drawing.
第１図は本発明の一実施例を説明する図であって、１は
アニール炉、２は石英ガラス管、３は電界印加装置、４
はリード線取出口、５は電界印加用電源である。電界印
加装置３により、高温アニール時に化合物半導体基板に
電界を印加する。電界の極性１強度は外部に設けた電界
印加用電源５により制御する。FIG. 1 is a diagram illustrating an embodiment of the present invention, in which 1 is an annealing furnace, 2 is a quartz glass tube, 3 is an electric field application device, and 4 is a diagram for explaining an embodiment of the present invention.
5 is a lead wire outlet, and 5 is a power source for applying an electric field. The electric field applying device 3 applies an electric field to the compound semiconductor substrate during high temperature annealing. The polarity 1 strength of the electric field is controlled by an external electric field application power source 5.
第２図は、第１図中の電界印加装置３の一実施例図であ
って、６はアルミナ製の電極ホルダ、７はモリブデン製
の負電極、８はモリブデン製の正電極、９は石英ガラス
製の負電極スペーサ、１０は石英ガラス製の正電極スペ
ーサ、１１は化合物半導体基板、１２は固定治具である
。正電極スペーサ１０と負電極スペーサ９は、放電防止
のために設置されているものである１本装置によるアニ
ール工程は、まず、予めイオン注入され、保護膜付の化
合物半導体基板を、イオン注入された基板面が正電極側
となるように、設定する。基板に対する電界Ｅの印加方
向を第３図に示す。ここで、１３は化合物半導体基板、
１４はイオン注入層、１５は保護膜。FIG. 2 is an embodiment of the electric field application device 3 in FIG. 1, in which 6 is an alumina electrode holder, 7 is a molybdenum negative electrode, 8 is a molybdenum positive electrode, and 9 is a quartz electrode. A negative electrode spacer made of glass, 10 a positive electrode spacer made of quartz glass, 11 a compound semiconductor substrate, and 12 a fixing jig. The positive electrode spacer 10 and the negative electrode spacer 9 are installed to prevent discharge.The annealing process using this device first involves removing ions from a compound semiconductor substrate that has been previously ion-implanted and has a protective film attached to it. Set the substrate so that the surface of the substrate facing the positive electrode is the positive electrode side. FIG. 3 shows the direction in which the electric field E is applied to the substrate. Here, 13 is a compound semiconductor substrate,
14 is an ion implantation layer, and 15 is a protective film.
１６はイオン注入した側の面である。Reference numeral 16 denotes the ion-implanted side surface.
次に、クロムと酸素を不純物として添加した半絶縁性Ｇ
ａＡｓ基板を例にとり、具体的数値例を挙げて説明する
。なお、インジウム添加の基板の場合にも、同様の結果
を得ている。第４図は、ｎ型不純物として２＊Ｓｉ＋イ
オンを加速エネルギ３０ｋｅＶ、ドープ量３Ｘ１０”ａ
ｎ−”で注入し、保護膜としてプラズマＣＶＤ （Ｃｈ
ｅｍｉｃａｌ ＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ、化学
的気相析出）法によりＳ ｉ Ｎ ｘ膜を積層した後、
８００℃、 １０分の温度条件、電界強度５５００Ｖ／
ａｍ （平行に配置された正、負両電極間電圧Ｖを両極
板間距離口で割算したもの）の電界条件でアニールした
時のキャリアプロファイルであり、電界印加の効果を示
すため、電界を印加しない時のキャリアプロファイルも
示しである。ここで保護膜の膜厚は１５００オングスト
ローム、積層温度は３８０℃である。測定は電解エッチ
形のＣ−■プロファイラにより行った。測定の結果、第
４図に示されるように、５５００Ｖ／ａｎの電界を印加
した場合には実線の曲線で示される結果が、また、電界
を印加しない場合には破線の曲線で示される結果が得ら
れた。これらの結果から、電界印加の場合の方が、注入
の深さが平均的に０．０１−浅くなることが判明した。Next, semi-insulating G with chromium and oxygen added as impurities
Taking an aAs substrate as an example, this will be explained by giving a specific numerical example. Note that similar results were obtained in the case of an indium-doped substrate. Figure 4 shows 2*Si+ ions as n-type impurities at an acceleration energy of 30 keV and a doping amount of 3×10”a.
n-” and plasma CVD (Ch
After laminating the SiNx film using the chemical vapor deposition method,
Temperature conditions: 800℃, 10 minutes, electric field strength: 5500V/
This is the carrier profile when annealing under the electric field condition of am (the voltage V between the positive and negative electrodes arranged in parallel divided by the distance between the two electrodes). The carrier profile when no voltage is applied is also shown. Here, the thickness of the protective film is 1500 angstroms, and the lamination temperature is 380°C. The measurement was carried out using an electrolytic etch type C-■ profiler. As a result of the measurement, as shown in Figure 4, when an electric field of 5500 V/an is applied, the result is shown by the solid line curve, and when no electric field is applied, the result is shown by the broken line curve. Obtained. From these results, it was found that the implantation depth was on average 0.01 mm shallower when an electric field was applied.
第５図は、クロム添加の３インチ径のＧａＡｓ基板によ
る。電界印加によりキャリアプロファイルの特性が向上
する領域を示す一例で、アニールは窒素雰囲気中、大気
圧下で行った。イオン注入条件は、加速エネルギが３０
〜７０ｋｅＶ、ドープ量が１×１０°〜３ ＸＩＯ”ａ
！１−”、注入したイオンは２８Ｓｊ＋である。第４図
より、アニール温度９００℃以上では活性化率が低下し
、良好なキャリアプロファイルが得られなかった。アニ
ール温度が９００℃〜６００℃の間では、電界強度２０
００Ｖ／■以上の電界印加で効果が現われ、２０００Ｖ
／ａｎ以下では効果は現われなかった。また、電界を強
くしすぎて、電界強度がほぼ６０００Ｖ／ｃｍ以上では
放電が生じた。アニール温度６００℃以下では電界印加
の効果が現われなかった。FIG. 5 is based on a 3 inch diameter GaAs substrate doped with chromium. This is an example showing a region where carrier profile characteristics are improved by applying an electric field, and annealing was performed in a nitrogen atmosphere at atmospheric pressure. The ion implantation conditions are acceleration energy of 30
~70keV, doping amount 1×10°~3XIO”a
! 1-", the implanted ions were 28Sj+. From Figure 4, when the annealing temperature was 900°C or higher, the activation rate decreased and a good carrier profile could not be obtained. When the annealing temperature was between 900°C and 600°C. Then, the electric field strength is 20
The effect appears when an electric field of 00V/■ or more is applied, and 2000V
No effect was observed below /an. Further, when the electric field was made too strong and the electric field strength was approximately 6000 V/cm or more, discharge occurred. At an annealing temperature of 600° C. or lower, no effect of electric field application appeared.
第４図、第５図に示す実験結果より、半絶縁性Ｇ ａ
Ａ ｓ基板に対しては、アニール温度範囲６００℃〜９
００℃、電界強度２０００ Ｖ ／ ａｍ以上でキャリ
アの深さ方向の分布形状の界面側へのシフトを制御でき
ることが明らかになった。From the experimental results shown in Figures 4 and 5, it is clear that semi-insulating Ga
For As substrates, the annealing temperature range is 600℃~9
It has become clear that the shift of the distribution shape of carriers in the depth direction toward the interface side can be controlled at 00°C and an electric field strength of 2000 V/am or higher.
なお、上記実施例においては、アニール保護膜としてＳ
ｉＮｘ膜を、基板として半絶縁性ＧａＡｓ基板を用いた
例について説明したが、本発明はこれらに限定されるも
のではなく、保護膜無しのアニールや、保護膜としてＳ
ｉｏ、、ＳｉＯｘＮｙ、高融点金属あるいはそのシリサ
イドあるいはその窒化物、基板として化合物半導体全般
に対しても十分適用できることは言うまでもない。また
、上記実施例では電界印加装置をアニール炉内に設置す
るとしたが、これは、基板とは離してアニール炉外部に
設置する構成とすることも可能である。In the above embodiment, S is used as the annealing protective film.
Although the iNx film has been described using an example in which a semi-insulating GaAs substrate is used as the substrate, the present invention is not limited thereto, and annealing without a protective film or S
io, SiOxNy, high melting point metals, silicides thereof, nitrides thereof, and as substrates, it goes without saying that the present invention is fully applicable to all compound semiconductors. Further, in the above embodiment, the electric field application device is installed inside the annealing furnace, but it can also be configured to be installed outside the annealing furnace and separated from the substrate.
次に１本発明アニール装置によりアニール処理して電界
効果トランジスタを作成する一例を、第６図（ａ）〜（
ｄ）に示す工程順の断面構造図により説明する。第６図
（ａ）において、半絶縁性Ｇ ａ Ａ ｓ基板１７にｚ
ａＳ４＋イオンを、加速エネルギ７０ｋｅＶ、ドープ量
１０１２〜１０１３ａｎ−”の条件で注入する。次に、
第６図（ｂ）に示すように、通常のフォトマスクを用い
たフォトエツチング技術によりゲート位置をマスクする
ためのストライプ状レジストパタン１８を形成する。こ
のパタン１８をマスクとして１９．２０の部分に選択的
に２８Ｓｊ“イオンを加速エネルギ２００ ｋ ｅ Ｖ
、ドープ量１０” 〜１０”ａｍ−”の条件で注入する
。本注入はゲート・ソース間およびゲート・ドレイン間
の直列抵抗を低減するために行う。レジストパタン１８
を除去した後、アニール保護膜ＳｉＮｘを１０００〜１
５００オングストロームの厚さに堆積し、本発明による
電界印加アニールを適用し、注入層を活性化する。アニ
ール条件は温度が８００℃、アニール時間が１０分、印
加電界の強度が５５００ Ｖ ／ ａｍである。その後
、保護膜を除去し、第６図（ｃ）に示すソース電極２２
、ドレイン電極２３をＡｕＧａ／Ｎｉなどの電極材によ
り形成し、第６図（ｄ）に示すゲート電極２４をＴｉ／
Ｍｏ／Ａｕなどの３Ｍ金属構成などで形成して、トラン
ジスタが完成する。Next, an example of fabricating a field effect transistor by annealing using the annealing apparatus of the present invention is shown in FIGS.
This will be explained with reference to the cross-sectional structure diagram of the process order shown in d). In FIG. 6(a), z is applied to the semi-insulating Ga As substrate 17.
aS4+ ions are implanted under the conditions of an acceleration energy of 70 keV and a doping amount of 1012 to 1013 an-''.Next,
As shown in FIG. 6(b), a striped resist pattern 18 for masking the gate position is formed by photoetching using a normal photomask. Using this pattern 18 as a mask, 28Sj" ions were selectively accelerated at a portion of 19.20 at an energy of 200 k e V.
, with a doping amount of 10" to 10"am-". This implantation is performed to reduce the series resistance between the gate and source and between the gate and drain. Resist pattern 18
After removing the annealing protective film SiNx,
Deposit to a thickness of 500 angstroms and apply an electric field anneal according to the invention to activate the injection layer. The annealing conditions are a temperature of 800 °C, an annealing time of 10 minutes, and an applied electric field strength of 5500 V/am. After that, the protective film is removed and the source electrode 22 shown in FIG. 6(c) is removed.
, the drain electrode 23 is formed of an electrode material such as AuGa/Ni, and the gate electrode 24 shown in FIG. 6(d) is formed of Ti/Ni.
A transistor is completed by forming a 3M metal composition such as Mo/Au.
以上説明したように、本発明によれば、ＧａＡｓなどの
化合物半導体基板のキャリアの分布を界面側に移動させ
ることができ、注入層を浅くすることが可能となった。As described above, according to the present invention, the distribution of carriers in a compound semiconductor substrate such as GaAs can be moved to the interface side, and the injection layer can be made shallow.
第１図は本発明装置の一実施例図、第２図は本発明にお
ける電界印加装置の一例を示す図、第３図は電界印加方
向の説明図、第４図は電界印加時と印加しない時とのキ
ャリアプロファイルの比較図、第５図はキャリアプロフ
ァイルが改善される領域を示す図、第６図（ａ）、（ｂ
）、（ｃ）、（ｄ）は本発明装置による電界効果トラン
ジスタ作成時の断面構造図を工程順に示す図である。
符号の説明
１・・・アニール炉 ２・・・石英ガラス３・・
・電界印加装置 ４・・・リード線取出口５・・・
電界印加用電源 ６・・・電極ホルダ７・・・負電極
８・・・正電極９・・・負電極スペーサ
１０・・・正電極スペーサ１１、１３・・・化合物半
導体基板
１２・・・固定治具 １４・・・イオン注入層
１５・・・保護膜
１６・・・イオン注入した側の面
１７・・・ＧａＡｓ基板 １８・・・マスクバタン
１９、２０．２１−ｎ型導電層
２２・・・ソース電極 ２３・・・ドレイン電極
２４・・・ゲート電極
特許出願人 日本電信電話株式会社
代理人弁理士 中村 純之助
才１ 凶
５−４ＸＥＰｔｌＪＩｆｉｉｌｉ＄
才２図
１−３図
１０−・−正雪掻ズヘ゛−４７１６−−−イオ〉ｊ主入
ＩＲイ璽り一面矛５ 図
了ニールン数序Ｔｔｋ（’ｃ）
３Ｐ６ へ１
（Ｃ１）
１７−４ａＡｓＬ抜
１８−−−マス２ハ改シ
＋９．２０．２１−一人＠４−電漕
２４・・−ゲート切シーたｒFig. 1 is a diagram showing an example of the device of the present invention, Fig. 2 is a diagram showing an example of the electric field applying device of the present invention, Fig. 3 is an explanatory diagram of the direction of electric field application, and Fig. 4 is a diagram showing when an electric field is applied and when no electric field is applied. Figure 5 is a diagram showing areas where the carrier profile is improved, Figures 6(a) and (b)
), (c), and (d) are diagrams illustrating cross-sectional structural views in the order of steps when producing a field effect transistor using the apparatus of the present invention. Explanation of symbols 1... Annealing furnace 2... Quartz glass 3...
・Electric field application device 4...Lead wire outlet 5...
Power supply for applying electric field 6... Electrode holder 7... Negative electrode 8... Positive electrode 9... Negative electrode spacer
10... Positive electrode spacers 11, 13... Compound semiconductor substrate 12... Fixing jig 14... Ion implanted layer 15... Protective film 16... Ion implanted side surface 17... GaAs substrate 18...Mask button 19, 20.21-N-type conductive layer 22...Source electrode 23...Drain electrode 24...Gate electrode Patent applicant Junnosuke Nakamura, Patent attorney representing Nippon Telegraph and Telephone Corporation 1 evil 5-4 1 (C1) 17-4aAsL removal 18---Mass 2ha change+9.20.21-One person @4-Electric row 24...-Gate cut seata r
Claims (1)
純物をアニールにより活性化させてそれぞれｐ型あるい
はｎ型導電層を形成するアニール装置において、上記基
板をアニールするアニール炉と、このアニール炉の内部
あるいは外部に設置されて上記基板に垂直に電界を印加
する電界印加装置とを備えたことを特徴とする化合物半
導体基板のアニール装置。 ２、前記電界印加装置は、前記基板のイオン注入された
面から裏側の面に向けて電界を印加する極性を備えた電
界印加装置であることを特徴とする特許請求の範囲第１
項記載の化合物半導体基板のアニール装置。 ３、前記アニール炉は、その炉内温度を少なくとも６０
０℃〜９００℃の範囲に制御可能なアニール炉であり、
前記電界印加装置は、平行に配置された正負両電極板間
の電界強度を少なくとも２，０００Ｖ／ｃｍ〜６，００
０Ｖ／ｃｍの範囲に制御可能な電界印加装置であること
を特徴とする特許請求の範囲第１項あるいは第２項記載
の化合物半導体基板のアニール装置。[Claims] 1. An annealing apparatus for activating p-type or n-type impurities implanted into a compound semiconductor substrate by annealing to form a p-type or n-type conductive layer, respectively, an annealing furnace for annealing the substrate. and an electric field application device installed inside or outside the annealing furnace to apply an electric field perpendicularly to the substrate. 2. Claim 1, wherein the electric field application device is an electric field application device with polarity that applies an electric field from the ion-implanted surface of the substrate to the back surface.
An annealing apparatus for a compound semiconductor substrate as described in 1. 3. The annealing furnace has an internal temperature of at least 60°C.
It is an annealing furnace that can be controlled in the range of 0°C to 900°C,
The electric field applying device sets the electric field strength between the positive and negative electrode plates arranged in parallel to at least 2,000 V/cm to 6,000 V/cm.
An annealing device for a compound semiconductor substrate according to claim 1 or 2, characterized in that the device is an electric field applying device that can be controlled within a range of 0 V/cm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28424586A JPS63138741A (en) | 1986-12-01 | 1986-12-01 | Annealing device for compound semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28424586A JPS63138741A (en) | 1986-12-01 | 1986-12-01 | Annealing device for compound semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63138741A true JPS63138741A (en) | 1988-06-10 |
Family
ID=17676039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28424586A Pending JPS63138741A (en) | 1986-12-01 | 1986-12-01 | Annealing device for compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63138741A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139394A2 (en) * | 2000-03-30 | 2001-10-04 | International Business Machines Corporation | Method and device for electric field assisted anneal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984787A (en) * | 1972-12-21 | 1974-08-14 | ||
| JPS5586123A (en) * | 1978-12-23 | 1980-06-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61178500A (en) * | 1985-01-31 | 1986-08-11 | マツクス‐プランク‐ゲゼルシヤフト・ツール・フエルデルング・デル・ヴイツセンシヤフテン・エー・フアウ | Conversion of local atomic composition of solid body, manufacture of semiconductor having locally different electroconductivities, polarization of semiconductor p-n junction, semiconductor-constitutional element, condensationfor matter and gas accumulator |
-
1986
- 1986-12-01 JP JP28424586A patent/JPS63138741A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984787A (en) * | 1972-12-21 | 1974-08-14 | ||
| JPS5586123A (en) * | 1978-12-23 | 1980-06-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61178500A (en) * | 1985-01-31 | 1986-08-11 | マツクス‐プランク‐ゲゼルシヤフト・ツール・フエルデルング・デル・ヴイツセンシヤフテン・エー・フアウ | Conversion of local atomic composition of solid body, manufacture of semiconductor having locally different electroconductivities, polarization of semiconductor p-n junction, semiconductor-constitutional element, condensationfor matter and gas accumulator |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139394A2 (en) * | 2000-03-30 | 2001-10-04 | International Business Machines Corporation | Method and device for electric field assisted anneal |
| SG100658A1 (en) * | 2000-03-30 | 2003-12-26 | Ibm | Dc or ac electric field business anneal |
| US6822311B2 (en) | 2000-03-30 | 2004-11-23 | International Business Machines Corporation | DC or AC electric field assisted anneal |
| EP1139394A3 (en) * | 2000-03-30 | 2006-02-15 | International Business Machines Corporation | Method and device for electric field assisted anneal |
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