JPH07321061A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH07321061A
JPH07321061A JP23898294A JP23898294A JPH07321061A JP H07321061 A JPH07321061 A JP H07321061A JP 23898294 A JP23898294 A JP 23898294A JP 23898294 A JP23898294 A JP 23898294A JP H07321061 A JPH07321061 A JP H07321061A
Authority
JP
Japan
Prior art keywords
insulating film
heating
film
semiconductor device
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23898294A
Other languages
Japanese (ja)
Inventor
Masaharu Hamazaki
正治 浜崎
Kazuo Nishiyama
和夫 西山
Hiroshi Yamamoto
博士 山本
Kazuhiro Tajima
和浩 田島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP23898294A priority Critical patent/JPH07321061A/en
Publication of JPH07321061A publication Critical patent/JPH07321061A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To improve the characteristics of an SiO2 film or the like using an IR annealing furnace, which has a very superior high-temperature and short-time controllability, in a method of manufacturing a semiconductor device, which has a process of forming an insulating film. CONSTITUTION:A method of manufacturing a semiconductor device is provided with a process of forming an insulating film, such as an SiO2 film, on a semiconductor substrate, such as an Si semiconductor substrate, in an atmosphere containing oxidizing gas or the like, such as chlorine gas, or the like, a process of heating the substrate and the insulating film in an N2 gas, O2 gas, inert gas or the like-containing atmosphere or the like by an IR heating method and a process of forming an electrode (an Al electrode or the like) on the insulating film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関するものである。本発明は例えばメモリー装置の製造
に適用することができ、その場合特に最近のMOSメモ
リー(DRAM,SRAM等)で要求されている薄いS
iO2 膜の特性を著しく改善できる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. The present invention can be applied, for example, to the manufacture of memory devices, in which case the thin S required especially in recent MOS memories (DRAM, SRAM, etc.) is required.
The properties of the iO 2 film can be significantly improved.

【0002】[0002]

【発明の概要】本発明は、半導体装置の製造方法におい
て、半導体基体上に絶縁膜を形成し、その後IR加熱に
より加熱処理を施すことにより、短時間の加熱によって
膜特性を著しく改善し得るようにしたものである。
SUMMARY OF THE INVENTION According to the present invention, in a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate and then heat treatment is performed by IR heating, so that the film characteristics can be remarkably improved by heating for a short time. It is the one.

【0003】[0003]

【従来の技術】最近の半導体装置、例えばMOSメモリ
ーは微細化が進み、スケーリング則に従ってゲート酸化
膜等は極めて薄くなってきている。
2. Description of the Related Art Recent semiconductor devices, such as MOS memories, have been miniaturized, and gate oxide films and the like have become extremely thin in accordance with scaling rules.

【0004】例えば256KDRAMでの容量酸化膜厚
は100〜120Åであり、1MbitDRAMでは8
0〜100Å程度の薄膜が望まれる。SRAMセルでの
酸化膜も同様であり、256KSRAMで200Å、1
MbitSRAMでは150Å以下が要求される。
For example, a 256K DRAM has a capacitance oxide film thickness of 100 to 120 Å, and a 1 Mbit DRAM has 8
A thin film of about 0 to 100Å is desired. The same applies to the oxide film in the SRAM cell, which is 200 Å for 256K SRAM, 1
The Mbit SRAM requires 150 Å or less.

【0005】一方この様な薄いSiO2 膜では耐圧の確
保が極めて重要であり、またSi表面のクリーニング処
理と共にSiO2 /Si界面の表面準位の低減も重要で
ある。
On the other hand, in such a thin SiO 2 film, it is extremely important to secure the breakdown voltage, and it is also important to reduce the surface level of the SiO 2 / Si interface together with the cleaning treatment of the Si surface.

【0006】即ち薄いSiO2 膜を形成するには通常9
00℃前後の酸化炉や酸素、窒素混合ガス(O2
2 )キャリアーを用いた実効的酸素分圧を低くした低
圧酸化法等によるが、これらの酸化法では酸化膜の緻密
性に問題があり、耐圧低下や界面準位の増加が懸念され
る。
That is, it is usually 9 to form a thin SiO 2 film.
Oxidation furnace at around 00 ° C and mixed gas of oxygen and nitrogen (O 2 +
Although a low pressure oxidation method using N 2 ) carrier and a low effective oxygen partial pressure is used, these oxidation methods have a problem in the denseness of an oxide film, and there is a concern that the breakdown voltage may decrease and the interface state may increase.

【0007】[0007]

【発明が解決しようとする問題点】上述したように、従
来より薄いSiO2 膜形成のために、低温・低圧酸化法
等が検討されているが、この方法により得られた膜はS
iO2 /Si界面にSiOx結合や未結合のSi原子が
存在し、これらが界面準位の増加、耐圧劣化の要因とな
り得ると言われている。
As described above, a low temperature / low pressure oxidation method or the like has been studied for forming a thinner SiO 2 film than before, but the film obtained by this method is S
It is said that SiOx bonds and unbonded Si atoms are present at the iO 2 / Si interface, and these can cause an increase in the interface state and a breakdown voltage deterioration.

【0008】また、高温処理によって膜特性の改善は図
れるが、従来の熱処理では処理時間が長い為に下地接合
形状が変化し三次元素子や微細MOS構造には適さな
い。
Further, although the film characteristics can be improved by the high temperature treatment, the conventional heat treatment is not suitable for a three-dimensional element or a fine MOS structure because the underlying bonding shape changes due to the long treatment time.

【0009】本発明は前述した問題点を改善すべく高
温、短時間の制御性の極めてすぐれたIRアニール炉を
用いて絶縁膜例えばSiO2 膜の特性を改善することを
目的とする。
It is an object of the present invention to improve the characteristics of an insulating film such as a SiO 2 film by using an IR annealing furnace which is excellent in controllability at high temperature for a short time in order to solve the above problems.

【0010】[0010]

【問題点を解決するための手段】上記目的は、半導体基
体上に酸化性ガスないしは塩素元素を含む雰囲気中等で
絶縁膜(例えばSiO2 )を形成し、その後、窒素、酸
素、不活性ガスの少なくとも一種を含む雰囲気中等でI
R加熱処理を施すことにより、達成される。IR加熱は
短時間でよい。本発明でいうIR加熱とは、ハロゲンラ
ンプ光等による加熱の他、直接試料に照射されるレーザ
ー光による該試料の加熱なども含まれる。
The above object is to form an insulating film (for example, SiO 2 ) on a semiconductor substrate in an atmosphere containing an oxidizing gas or chlorine element, and then to remove nitrogen, oxygen, and an inert gas. I in an atmosphere containing at least one
This is achieved by applying R heat treatment. IR heating may be short. The IR heating referred to in the present invention includes not only heating by a halogen lamp light or the like, but also heating of the sample by a laser beam directly applied to the sample.

【0011】本発明の構成を具体的に略述すると以下の
様である。即ち例えば酸化性ガスや、塩素元素を含む雰
囲気中での処理により酸化膜成長させて絶縁膜を形成し
た半導体ウェハーに対し、高出力のハロゲンランプ光等
をウェハーに均一に照射し、瞬間的に加熱するように構
成できる。
The structure of the present invention is specifically outlined as follows. That is, for example, a semiconductor wafer on which an oxide film has been grown by treatment in an atmosphere containing an oxidizing gas or chlorine element to form an insulating film is uniformly irradiated with high-output halogen lamp light, etc. It can be configured to heat.

【0012】[0012]

【作用】本発明において、例えばSiO2 膜成長後、高
温のIR加熱を施すことにより、SiO2 −Si界面の
未結合Si−Oボンドを十分なSiO2 結合とすること
ができ、これにより界面特性が改善された半導体装置を
得ることができる。また、このIR加熱は短時間で行え
るので、これにより、例えば三次元素子や微細MOS等
で問題となる下地接合形状の変化による特性劣化が防止
された。
In the present invention, the unbonded Si—O bond at the SiO 2 —Si interface can be made into a sufficient SiO 2 bond by subjecting the SiO 2 film to IR heating at a high temperature after the growth of the SiO 2 film. A semiconductor device having improved characteristics can be obtained. Further, since this IR heating can be performed in a short time, the characteristic deterioration due to the change of the underlying bonding shape, which is a problem in a three-dimensional element or a fine MOS, can be prevented.

【0013】[0013]

【実施例】以下に本発明の実施例を詳述する。なお、当
然のことながら本発明は以下に述べる実施例に限定され
るものではない。
EXAMPLES Examples of the present invention will be described in detail below. Naturally, the present invention is not limited to the embodiments described below.

【0014】実施例1 本実施例においては、半導体基体(ここではSi基板)
上に絶縁膜(ここではSiO2 膜)を形成する工程と、
IR加熱法により該半導体基体と該絶縁膜を加熱する工
程と、上記絶縁膜上に電極(ここではAl電極)を形成
する工程とにより、半導体装置を製造した。
Example 1 In this example, a semiconductor substrate (here, a Si substrate) is used.
A step of forming an insulating film (here, a SiO 2 film),
A semiconductor device was manufactured by a step of heating the semiconductor substrate and the insulating film by an IR heating method and a step of forming an electrode (here, an Al electrode) on the insulating film.

【0015】特に実施例の絶縁膜は、酸化性ガスによっ
て、特に塩素元素を含む雰囲気中で上記半導体基体表面
を酸化することにより形成した。
In particular, the insulating film of the examples was formed by oxidizing the surface of the semiconductor substrate with an oxidizing gas, especially in an atmosphere containing chlorine element.

【0016】また、上記IR加熱法により該半導体基体
と該絶縁膜を加熱する工程は、窒素、酸素、不活性ガス
の少なくとも一種を含む雰囲気(本例ではN2 雰囲気)
中で行った。
Further, in the step of heating the semiconductor substrate and the insulating film by the IR heating method, the atmosphere containing at least one of nitrogen, oxygen and an inert gas (N 2 atmosphere in this example)
Went inside.

【0017】更に詳しくは、本実施例においては、実験
サンプルとしてCZ(100)n−type基板(2〜
3ohm−cm)を用い、これに1100℃,O2 +H
Cl(1%)の雰囲気中でゲート酸化膜(SiO2 )を
900Å成長させた。次に、SiO2 膜のPOA(Po
st−Oxidation−Anneal)処理として
2 雰囲気中で1000〜1150℃、1秒〜2分のI
Rアニール(ここではハロゲンランプ加熱)処理を施し
た。この後Al蒸着、メタルシンター(400℃、60
分)を行い、MOSキャパシターを作成した。
More specifically, in this embodiment, as an experimental sample, a CZ (100) n-type substrate (2 to
3 ohm-cm), and at 1100 ° C., O 2 + H
A gate oxide film (SiO 2 ) of 900 Å was grown in an atmosphere of Cl (1%). Then, POA of the SiO 2 film (Po
st-Oxidation-anneal) treatment in an N 2 atmosphere at 1000 to 1150 ° C. for 1 second to 2 minutes
R annealing (here, halogen lamp heating) treatment was performed. After this, Al vapor deposition, metal sintering (400 ℃, 60
Min) to prepare a MOS capacitor.

【0018】図1に、IRアニール処理温度がそれぞれ
1000℃(図中、線IIIで示す)、1100℃
(同、線Iで示す)、1150℃(同、線IIで示す)
における処理時間と表面電荷Nss(cm-2eV-1)の
関係を示す。
In FIG. 1, the IR annealing temperature is 1000 ° C. (indicated by line III in the figure) and 1100 ° C., respectively.
(The same is shown by line I) 1150 ° C. (the same is shown by line II)
The relationship between the processing time and the surface charge Nss (cm −2 eV −1 ) in FIG.

【0019】図1から明らかなように、線I及び線II
で示した1100℃及び1150℃のIRアニール処理
を施した本発明によるサンプルのNss値は、線III
で示した1000℃処理サンプルのNss値よりも低
く、より優れた界面特性を有することがわかる。また1
100℃以上のIRアニール処理を施した本発明による
サンプルのNss値は、瞬間的に0.6〜1×109
-2eV-1となり、処理時間0で示されるPOA処理無
のサンプル(Nss=5.9×109 cm-2eV)と比
較して1/5〜1/10に低減されていることがわか
る。
As is apparent from FIG. 1, line I and line II
The Nss value of the sample according to the present invention which was subjected to the IR annealing treatment at 1100 ° C. and 1150 ° C.
It can be seen that the Nss value is lower than that of the 1000 ° C.-treated sample shown in FIG. Again 1
The Nss value of the sample according to the present invention that has been subjected to IR annealing at 100 ° C. or higher has an instantaneous Nss value of 0.6 to 1 × 10 9 c.
m −2 eV −1 , which is reduced to ⅕ to 1/10 as compared with the sample without POA treatment (Nss = 5.9 × 10 9 cm −2 eV), which shows the treatment time of 0. I understand.

【0020】図2は上述したと同様に成長させたSiO
2 膜のPOA処理をウェットO2 (図中、線IVで示し
た)及びドライO2 (同、線Vで示した)の雰囲気中、
1000℃の電気炉で行った比較例であるが1×109
cm -2 eV-1のNssを得るには60分以上を要して
おり、この条件では三次元素子接合や微細MOSでのウ
ェル層、チャネルストップ領域等、ゲート酸化膜成長時
にすでに形成されている接合は大きく再分布してしま
い、これに比べて図1における線I及び線IIで示した
本発明によるサンプルは瞬間的にNss値が1×10-9
cm -2 eV-1以下に低下し、短時間のIRアニール処
理による本発明によれば膜特性が著しく改善されること
が明らかである。
FIG. 2 shows SiO grown as described above.
The POA treatment of the two films was performed in an atmosphere of wet O 2 (shown by line IV in the figure) and dry O 2 (shown by line V in the figure).
This is a comparative example conducted in an electric furnace at 1000 ° C., but 1 × 10 9
It takes more than 60 minutes to obtain Nss of cm −2 eV −1 , and under these conditions, the three-dimensional element junction, the well layer in the fine MOS, the channel stop region, etc. are already formed during the growth of the gate oxide film. The existing junctions were largely redistributed, and in comparison with this, the samples according to the present invention shown by lines I and II in FIG. 1 had an instantaneous Nss value of 1 × 10 −9.
It is clear that the film characteristics are significantly improved according to the present invention by the IR annealing treatment for a short time, which is lower than cm -2 eV -1 .

【0021】実施例2 実施例1と同じCZ(100)n−type2〜3oh
m−cmのSi基板を用い、約150Åの薄いSiO2
膜を形成した。その後N2 雰囲気中で1100℃、10
秒のIRアニールによるPOA処理を行った場合の耐圧
分布を図3に示した。また比較例として、同様のSiO
2 膜を900℃スチーム処理したものの耐圧分布を図4
に示した。図3及び図4はともに横軸に膜破壊のために
かけた電場、縦軸に破壊割合をとっている。図3に示さ
れる本発明による試料は、図中(イ)で示される破壊電
界場9〜10MV/cm付近で集中的に膜破壊が起きて
おり、図4に示される比較試料の図中(ロ)で示される
8.5〜9.5MV/cmに比べ、高電界場側に移動し
ていることがわかる。また、本発明によるIRアニール
処理したものの方が耐圧分布の集中性がみられ、ウェハ
ーの面内均一性が向上していることがわかる。
Example 2 Same as Example 1 CZ (100) n-type2-3 oh
Using m-cm Si substrate, thin SiO 2 of about 150Å
A film was formed. After that, in a N 2 atmosphere, 1100 ° C., 10
FIG. 3 shows the breakdown voltage distribution when the POA treatment by IR annealing for 2 seconds was performed. As a comparative example, similar SiO
Figure 4 shows the breakdown voltage distribution of two films that have been steam treated at 900 ° C.
It was shown to. In both FIG. 3 and FIG. 4, the horizontal axis represents the electric field applied for film destruction, and the vertical axis represents the breakdown rate. In the sample according to the present invention shown in FIG. 3, film breakdown occurs intensively in the vicinity of the breakdown electric field field of 9 to 10 MV / cm shown in (a) in the figure, and in the figure of the comparative sample shown in FIG. It can be seen that, as compared with 8.5 to 9.5 MV / cm shown in (b), it moves to the high electric field side. Further, it can be seen that the IR annealed according to the present invention shows a more concentrated concentration of the breakdown voltage distribution, and the in-plane uniformity of the wafer is improved.

【0022】なお、上記IRアニール処理の雰囲気はN
2 中の他、O2 中、N2 +O2 中及びAr中等で行うこ
とができる。また、IR加熱は、高出力のハロゲンラン
プ光の他に9−10μm波長CO2 レーザー光照射によ
ってSi−Oの固有吸収ピークとマッチングさせSiO
2 /Si界面を瞬間的に加熱しても良い。
The atmosphere of the IR annealing treatment is N
Other 2, in O 2, can be carried out in N 2 + O 2 and Ar secondary. In addition, IR heating is performed by irradiating a CO 2 laser beam with a wavelength of 9-10 μm in addition to a high-output halogen lamp light to match the intrinsic absorption peak of Si—O with SiO.
The 2 / Si interface may be heated instantaneously.

【0023】[0023]

【発明の効果】上述したように、本発明によれば、高
温、短時間の制御性の極めてすぐれたIRアニール炉を
用いてPOA処理することにより、下地接合を変化する
事なくSiO2 膜の特性の改善が達せられる。
As described above, according to the present invention, the POA process is performed by using the IR annealing furnace which is excellent in controllability at high temperature and for a short time, so that the SiO 2 film can be formed without changing the underlying bond. Improved properties can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る実施例におけるIRアニール処理
時間とNssとの関係を示す図である。
FIG. 1 is a diagram showing a relationship between IR annealing treatment time and Nss in an example according to the present invention.

【図2】比較例のPOA処理時間とNssとの関係を示
す図である。
FIG. 2 is a diagram showing a relationship between POA processing time and Nss in a comparative example.

【図3】本発明に係る実施例におけるIRアニール処理
試料の耐圧分布を示す図である。
FIG. 3 is a diagram showing a withstand voltage distribution of an IR-annealed sample in an example according to the present invention.

【図4】比較例の耐圧分布を示す図である。FIG. 4 is a diagram showing a breakdown voltage distribution of a comparative example.

【符号の説明】[Explanation of symbols]

I ……1100℃でIRアニール処理した試料 II ……1150℃でIRアニール処理した試料 III……1000℃でIRアニール処理した試料 IV ……ウェットO2 中でPOA処理した試料 V ……ドライO2 中でPOA処理した試料 (イ)……本発明による試料の集中膜破壊部分 (ロ)……比較試料の集中膜破壊部分I: Sample subjected to IR annealing at 1100 ° C. II: Sample subjected to IR annealing at 1150 ° C. III: Sample subjected to IR annealing at 1000 ° C. IV: Sample subjected to POA treatment in wet O 2 V: Dry O Sample subjected to POA treatment in 2 (a) ...... Concentrated film destruction part of sample according to the present invention (b) …… Concentrated film destruction part of comparative sample

───────────────────────────────────────────────────── フロントページの続き (72)発明者 田島 和浩 東京都品川区北品川6丁目7番35号 ソニ ー株式会社内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kazuhiro Tajima 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】半導体基体上に絶縁膜を形成する工程と、
IR加熱法により該半導体基体と該絶縁膜を加熱する工
程と、上記絶縁膜上に電極を形成する工程とからなる半
導体装置の製造方法。
1. A step of forming an insulating film on a semiconductor substrate,
A method of manufacturing a semiconductor device, comprising: a step of heating the semiconductor substrate and the insulating film by an IR heating method; and a step of forming an electrode on the insulating film.
【請求項2】請求項1記載の半導体装置の製造方法にお
いて、上記絶縁膜は酸化性ガスによって上記半導体基体
表面を酸化することにより形成されることを特徴とする
半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed by oxidizing the surface of the semiconductor substrate with an oxidizing gas.
【請求項3】請求項1記載の半導体装置の製造方法にお
いて、上記IR加熱法により該半導体基体と該絶縁膜を
加熱する工程は、窒素、酸素、不活性ガスの少なくとも
一種以上を含む雰囲気中で行われることを特徴とする半
導体装置の製造方法。
3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of heating the semiconductor substrate and the insulating film by the IR heating method is performed in an atmosphere containing at least one of nitrogen, oxygen and an inert gas. A method of manufacturing a semiconductor device, comprising:
【請求項4】半導体基体上に絶縁膜を形成する工程と、
窒素、酸素、不活性ガスの少なくとも一種を含む雰囲気
中でIR加熱法により該半導体基体と該絶縁膜を加熱す
る工程とからなる半導体装置の製造方法。
4. A step of forming an insulating film on a semiconductor substrate,
A method of manufacturing a semiconductor device, comprising a step of heating the semiconductor substrate and the insulating film by an IR heating method in an atmosphere containing at least one of nitrogen, oxygen and an inert gas.
【請求項5】半導体基体上に塩素元素を含む雰囲気中で
絶縁膜を形成する工程と、IR加熱法により該半導体基
体と該絶縁膜を加熱する工程とからなる半導体装置の製
法方法。
5. A method of manufacturing a semiconductor device, comprising the steps of forming an insulating film on a semiconductor substrate in an atmosphere containing chlorine element, and heating the semiconductor substrate and the insulating film by an IR heating method.
JP23898294A 1994-10-03 1994-10-03 Manufacture of semiconductor device Pending JPH07321061A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23898294A JPH07321061A (en) 1994-10-03 1994-10-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23898294A JPH07321061A (en) 1994-10-03 1994-10-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH07321061A true JPH07321061A (en) 1995-12-08

Family

ID=17038178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23898294A Pending JPH07321061A (en) 1994-10-03 1994-10-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH07321061A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144016A (en) * 1995-12-15 2001-05-25 Semiconductor Energy Lab Co Ltd Producing method for semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915910A (en) * 1972-06-07 1974-02-12
JPS53105975A (en) * 1977-02-28 1978-09-14 Toshiba Corp Heat treatment for silicon oxide film
JPS5513951A (en) * 1978-07-18 1980-01-31 Fujitsu Ltd Manufacturing method of semiconductor device
JPS5586123A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Manufacture of semiconductor device
JPS5898933A (en) * 1981-12-09 1983-06-13 Seiko Epson Corp Manufacture of semiconductor device
JPS59175129A (en) * 1983-03-23 1984-10-03 Nec Corp Manufacture of semiconductor device
JPS6187342A (en) * 1984-10-05 1986-05-02 Nec Corp Nitriding method of si by multiple-beam projection
JPS61124140A (en) * 1984-11-21 1986-06-11 Hitachi Ltd Method of forming oxide film

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915910A (en) * 1972-06-07 1974-02-12
JPS53105975A (en) * 1977-02-28 1978-09-14 Toshiba Corp Heat treatment for silicon oxide film
JPS5513951A (en) * 1978-07-18 1980-01-31 Fujitsu Ltd Manufacturing method of semiconductor device
JPS5586123A (en) * 1978-12-23 1980-06-28 Fujitsu Ltd Manufacture of semiconductor device
JPS5898933A (en) * 1981-12-09 1983-06-13 Seiko Epson Corp Manufacture of semiconductor device
JPS59175129A (en) * 1983-03-23 1984-10-03 Nec Corp Manufacture of semiconductor device
JPS6187342A (en) * 1984-10-05 1986-05-02 Nec Corp Nitriding method of si by multiple-beam projection
JPS61124140A (en) * 1984-11-21 1986-06-11 Hitachi Ltd Method of forming oxide film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144016A (en) * 1995-12-15 2001-05-25 Semiconductor Energy Lab Co Ltd Producing method for semiconductor device

Similar Documents

Publication Publication Date Title
US6190973B1 (en) Method of fabricating a high quality thin oxide
CA1297764C (en) Fabrication of devices having thin dielectric layers
JP2002353218A (en) Method for improved plasma nitridation of ultra thin gate dielectric
JPS6369238A (en) Method of forming silicon oxynitride thin film showing high breakdown voltage
JPS59213137A (en) Method of producing semiconductor device
EP0167208B1 (en) A method for growing an oxide layer on a silicon surface
JPH0770535B2 (en) Method for manufacturing semiconductor device
JPH07321061A (en) Manufacture of semiconductor device
JPH02135759A (en) Semiconductor device and manufacture thereof
JPS6223453B2 (en)
KR20000021246A (en) Method for forming insulating film for semiconductor device using deuterium oxide or deuterium
JPH0242725A (en) Manufacture of semiconductor device
JPH03280471A (en) Manufacture of semiconductor device
JPS5812732B2 (en) Manufacturing method for semiconductor devices
JP2917303B2 (en) Method for manufacturing semiconductor device
JP2693046B2 (en) Method for manufacturing semiconductor device
JPH09260372A (en) Manufacture of insulating film of semiconductor device
KR102146864B1 (en) Methods of forming semiconductor device
JPH07221092A (en) Manufacture of semiconductor device
Banholzer et al. Chlorine levels in SiO2 formed using TCA and LPCVD at low temperatures
JP3139835B2 (en) Method for manufacturing semiconductor device
KR100230395B1 (en) Forming method of semiconductor capacitor
JPH0336312B2 (en)
JPH05267284A (en) Manufacture of semiconductor device
JPH0516174B2 (en)