JPS6223453B2 - - Google Patents
Info
- Publication number
- JPS6223453B2 JPS6223453B2 JP54029981A JP2998179A JPS6223453B2 JP S6223453 B2 JPS6223453 B2 JP S6223453B2 JP 54029981 A JP54029981 A JP 54029981A JP 2998179 A JP2998179 A JP 2998179A JP S6223453 B2 JPS6223453 B2 JP S6223453B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- substrate
- sio
- gaas
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000010406 interfacial reaction Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 20
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
Landscapes
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
この発明は、半導体表面に絶縁膜を形成し、こ
れを半導体表面のパツシベーシヨンあるいはゲー
ト絶縁膜として利用する半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which an insulating film is formed on a semiconductor surface and used as a passivation film on the semiconductor surface or as a gate insulating film.
説明の都合上、以下半導体として特にシリコン
（Si）または砒化ガリウム（GaAs）を使用する２
つの場合を例にとり、まず従来技術について説明
する。 For convenience of explanation, silicon (Si) or gallium arsenide (GaAs) will be used as the semiconductor in the following.
Taking two cases as an example, the prior art will be explained first.
(1) Si基板の場合
(A) Si基板の表面に形成される絶縁膜として
は、従来熱酸化SiO2が標準的に用いられて
きた。すなわち、第１図ａのSi基板１を1000
℃程度の高温下で酸素または水蒸気中におく
と、第１図ｂのように表面に絶縁膜２が生成
される。熱酸化SiO2は全体として膜質は緻
密であるが、SiO2／Siの界面で酸化反応が進
行するため、界面に未反応Si３が残り、これ
が固定電荷としてデバイス特性に悪影響を与
える欠点がある。(1) In the case of a Si substrate (A) As an insulating film formed on the surface of a Si substrate, thermally oxidized SiO 2 has conventionally been used as a standard. That is, the Si substrate 1 in Fig. 1a is 1000
When placed in oxygen or water vapor at a high temperature of about .degree. C., an insulating film 2 is formed on the surface as shown in FIG. 1b. Thermally oxidized SiO 2 has a dense film quality as a whole, but since the oxidation reaction proceeds at the SiO 2 /Si interface, unreacted Si3 remains at the interface, which has the drawback of adversely affecting device characteristics as a fixed charge.
(B) 一方、他の従来例として、第２図ａのSi基
板１上に400℃あるいはそれ以下の低温で、
第２図ｂのように化学蒸着（CVD）により
SiO2の絶縁膜２′を形成させるときは界面で
の未反応Si３は無いが、膜質が緻密でなく、
このため、これを緻密化するために、例えば
第２図ｃのように900℃程度の高温で30分程
度の通常のアニールを行うと界面反応が起
り、第１図の場合と同様に未反応Si３が残
り、また、汚染不純物等が拡散するおそれが
ある。 (B) On the other hand, as another conventional example, on the Si substrate 1 shown in Fig. 2a,
By chemical vapor deposition (CVD) as shown in Figure 2b.
When forming the SiO 2 insulating film 2', there is no unreacted Si3 at the interface, but the film quality is not dense and
Therefore, in order to densify this, for example, if normal annealing is performed at a high temperature of about 900°C for about 30 minutes as shown in Figure 2c, an interfacial reaction will occur, and as in the case of Figure 1, unreacted There is a risk that Si3 will remain and contaminant impurities will be diffused.
(2) GaAs基板の場合
GaAs基板は高温で分解しやすいため、絶縁
膜の形成には従来主として500℃程度以下の低
温で行えるグロー放電酸化法、陽極酸化法、
CVD法などが用いられ、第３図ａのGaAs基板
１１上にGaAsの酸化物もしくはSiO2等の絶縁
膜１２′を第３図ｂのように形成する。しか
し、そのままでは絶縁膜１２′が緻密でないの
で800℃以上の温度でアニールを行い緻密化を
はかつている。しかしながらその際、GaAs基
板１１表面からのAsの蒸発やGaの外方拡散が
起つて、第３図ｃのようにGaAs基板１１表面
に変成層１３が形成されるので、多量の界面準
位や表面容量−電圧特性のヒステリシスが発生
する。このため、GaAs基板１１の表面への絶
縁膜１２の形成にはいまだに完全な方法が行わ
れていない。(2) In the case of GaAs substrates GaAs substrates are easily decomposed at high temperatures, so insulating films have traditionally been formed using glow discharge oxidation, anodic oxidation and
A CVD method or the like is used to form an insulating film 12' of GaAs oxide or SiO 2 on the GaAs substrate 11 shown in FIG. 3a, as shown in FIG. 3b. However, since the insulating film 12' is not dense as it is, it is annealed at a temperature of 800° C. or higher to make it denser. However, at this time, evaporation of As from the surface of the GaAs substrate 11 and outward diffusion of Ga occur, forming a metamorphic layer 13 on the surface of the GaAs substrate 11 as shown in FIG. Hysteresis occurs in the surface capacitance-voltage characteristics. For this reason, no perfect method has yet been used to form the insulating film 12 on the surface of the GaAs substrate 11.
この発明は上記の欠点を解消するためになされ
たものである。以下この発明について説明する。 This invention has been made in order to eliminate the above-mentioned drawbacks. This invention will be explained below.
(1) Si基板の場合
第４図ａのSi基板１の表面に通常のCVD・
SiO2膜、例えばモノシラン（SiH4）と酸素の気
相反応により400℃あるいはそれ以下の温度で
生成されるSiO2の絶縁膜２′を第４図ｂのよう
に1000Å程度の所望の厚さに形成した後、これ
にエネルギー密度0.6J／cm2、パルス幅0.1μｓ
程度の、例えばNd−YAGレーザー光または電
子線等のパルスを照射するもので、これにより
試料表面温度は瞬間的に1000℃まで上昇し、
SiO2の絶縁膜２′の緻密化した絶縁膜２が得ら
れる。しかもパルス照射後は試料温度は１μｓ
以内に700℃以下、１ｍｓ以内に100℃以下に下
がるので、1000℃でもSiの初期酸化反応の速度
定度は10-3μｍ／minであることを考えると、
このような短時間では従来のように未反応Si３
を生成させるような界面反応は進行せず、従つ
て界面電荷の発生はない。このため、上記の方
法により第４図ｃのようにSi基板１の表面に緻
密で、かつ界面電荷のないSiO2の絶縁膜２を
形成することができる。(1) In the case of a Si substrate The surface of the Si substrate 1 in Figure 4a is
A SiO 2 film, such as an SiO 2 insulating film 2' produced at a temperature of 400°C or lower by a gas phase reaction of monosilane (SiH 4 ) and oxygen, is deposited to a desired thickness of about 1000 Å as shown in Figure 4b. After forming the
This method irradiates a sample with a pulse of Nd-YAG laser light or an electron beam, which instantly raises the sample surface temperature to 1000℃.
A dense insulating film 2 of SiO 2 insulating film 2' is obtained. Moreover, the sample temperature is 1 μs after pulse irradiation.
Considering that the rate constant of the initial oxidation reaction of Si is 10 -3 μm/min even at 1000°C, the temperature decreases to below 700°C within 1 ms and below 100°C within 1 ms.
In such a short time, unreacted Si3
No interfacial reaction that would produce , therefore no interfacial charge is generated. Therefore, by the above method, it is possible to form a dense insulating film 2 of SiO 2 on the surface of the Si substrate 1 and free of interfacial charges, as shown in FIG. 4c.
(2) GaAs基板の場合
GaAs基板の場合も前述の方法を適用するも
ので、図面はSi基板の第４図を共用する。まず
第４図ａのGaAs基板１１の表面に界面反応の
起らない十分低温で形成できるCVD・SiO2
膜、スピン・オン・コーテイングSiO2膜等の
絶縁膜１２′を第４図ｂのように所望の膜厚ま
で形成し、次いで、前述と同程度の出力のレー
ザー光パルス等で照射すれば、前述と同程度の
短時間のみ表面を1000℃程度に昇温させること
が可能で、この間に従来のような変成層１３が
形成されるような反応は起らないので、第４図
ｃのように界面構造が良好で、かつ膜質も緻密
な絶縁膜１２をGaAs基板１１の表面に得るこ
とができる。(2) In the case of a GaAs substrate The above-mentioned method is also applied to the case of a GaAs substrate, and FIG. 4 for the Si substrate is used in common. First, CVD/SiO 2 can be formed on the surface of the GaAs substrate 11 shown in FIG.
If an insulating film 12' such as a spin-on coating SiO 2 film or the like is formed to a desired thickness as shown in FIG. It is possible to raise the temperature of the surface to about 1000°C for a short period of time similar to that described above, and during this time no reaction that would form the metamorphic layer 13 as in the past occurs, so the temperature rises as shown in Figure 4c. An insulating film 12 having a good interface structure and dense film quality can be obtained on the surface of the GaAs substrate 11.
以上説明したようにこの発明は、Siまたは
GaAs等の半導体表面に界面反応を起さない低温
度で絶縁膜を形成し、この絶縁膜と半導体表面と
の間に界面反応を進行させない短期間のレーザー
光または電子線等のエネルギー線のパルスを照射
することにより半導体表面に緻密でかつ界面特性
の良い優れた絶縁膜を形成することができる。こ
のため広く半導体装置の製造に適用でき、工業上
重要な価値を有する。 As explained above, this invention
Forms an insulating film on the surface of a semiconductor such as GaAs at a low temperature that does not cause an interfacial reaction, and short-term pulses of energy beams such as laser light or electron beams that do not cause an interfacial reaction between the insulating film and the semiconductor surface. By irradiating with , it is possible to form an excellent insulating film that is dense and has good interfacial properties on the semiconductor surface. Therefore, it can be widely applied to the manufacture of semiconductor devices and has important industrial value.
第１図、第２図、第３図は従来の半導体装置の
製造工程図、第４図はこの発明の一実施例を示す
製造工程図である。
図中、１はSi基板、２は緻密化したSiO2の絶縁
膜、２′は低温度で形成したSiO2の絶縁膜、１１
はGaAs基板、１２は緻密化した絶縁膜、１２′は
低温度で形成した絶縁膜である。
1, 2, and 3 are manufacturing process diagrams of a conventional semiconductor device, and FIG. 4 is a manufacturing process diagram showing an embodiment of the present invention. In the figure, 1 is a Si substrate, 2 is a densified SiO 2 insulating film, 2' is an SiO 2 insulating film formed at low temperature, and 11
12 is a GaAs substrate, 12 is a dense insulating film, and 12' is an insulating film formed at low temperature.
Claims (1)
縁膜を形成し、この絶縁膜に前記半導体表面との
間に界面反応を進行させない短時間でエネルギー
線を照射して前記絶縁膜を緻密化し、かつ良好な
界面特性を得る工程を含むことを特徴とする半導
体装置の製造方法。1. An insulating film is formed on the semiconductor surface at a low temperature that does not cause an interfacial reaction, and the insulating film is densified by irradiating the insulating film with energy rays for a short time that does not cause an interfacial reaction with the semiconductor surface. A method for manufacturing a semiconductor device, comprising the steps of: and obtaining good interface characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2998179A JPS55123133A (en) | 1979-03-16 | 1979-03-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2998179A JPS55123133A (en) | 1979-03-16 | 1979-03-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55123133A JPS55123133A (en) | 1980-09-22 |
| JPS6223453B2 true JPS6223453B2 (en) | 1987-05-22 |
Family
ID=12291129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2998179A Granted JPS55123133A (en) | 1979-03-16 | 1979-03-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55123133A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5898933A (en) * | 1981-12-09 | 1983-06-13 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS60211843A (en) * | 1984-04-05 | 1985-10-24 | Fuji Electric Corp Res & Dev Ltd | Forming method of insulating film pattern |
| JPS60211844A (en) * | 1984-04-05 | 1985-10-24 | Fuji Electric Corp Res & Dev Ltd | Forming method of insulating film |
| JP4782069B2 (en) * | 2007-05-09 | 2011-09-28 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor integrated circuit device |
| JP4782070B2 (en) * | 2007-05-09 | 2011-09-28 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device and manufacturing method thereof |
| JP2011228718A (en) * | 2011-05-23 | 2011-11-10 | Renesas Electronics Corp | Semiconductor integrated circuit device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4836599A (en) * | 1971-09-13 | 1973-05-30 | ||
| JPS5352058A (en) * | 1976-10-22 | 1978-05-12 | Hitachi Ltd | Formation of p-type layer |
-
1979
- 1979-03-16 JP JP2998179A patent/JPS55123133A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4836599A (en) * | 1971-09-13 | 1973-05-30 | ||
| JPS5352058A (en) * | 1976-10-22 | 1978-05-12 | Hitachi Ltd | Formation of p-type layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55123133A (en) | 1980-09-22 |
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