JPS6041849B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS6041849B2 JPS6041849B2 JP16163978A JP16163978A JPS6041849B2 JP S6041849 B2 JPS6041849 B2 JP S6041849B2 JP 16163978 A JP16163978 A JP 16163978A JP 16163978 A JP16163978 A JP 16163978A JP S6041849 B2 JPS6041849 B2 JP S6041849B2
- Authority
- JP
- Japan
- Prior art keywords
- manufacturing
- substrate
- semiconductor substrate
- semiconductor device
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、更に詳しくは半
導体基板に絶縁膜を形成した場合に生する絶縁膜中の固
定電荷や境界部分の界面準位を除去するための方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device, and more specifically, a method for removing fixed charges in an insulating film and interface states at boundaries that occur when an insulating film is formed on a semiconductor substrate. Regarding the method.
一般にＭＩＳ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｓｉ
ｌｉｃｏｎ）トランジスタにおいてはシリコン（Ｓｉ）
基板に二酸化硅素（ＳｉＯ０）膜を被着し、その上に金
属電極が形成された構造となつている。Generally MIS (Metal-Insulator-Si)
Silicon (Si) in transistors
It has a structure in which a silicon dioxide (SiO0) film is deposited on a substrate, and a metal electrode is formed on the film.
このような構造においてはＳｉ基板とＳｉＯ２膜の境界
部分には例えば１０″゜Ｃｍ−”ｅＶ−”程度の界面準
位が生じており、ＭＩＳトランジスタの製造工程におい
てさらにイオン注入やスパッタ蒸着等を行なうことによ
つて界面準位は１０″゛α−’ｅＶ−”程度に増加する
。In such a structure, an interface level of, for example, about 10"Cm-"eV-" is generated at the boundary between the Si substrate and the SiO2 film, and further ion implantation, sputter deposition, etc. are required in the manufacturing process of MIS transistors. By doing so, the interface level increases to about 10''α-'eV-''.
このような界面準位の存在はＭＩＳトランジスタの閾値
電圧Ｖｔｈの制御性を悪くし移動度を下けるため好まし
くないのでこれを除去する方法がいくつか提案されてい
る。The presence of such an interface state is undesirable because it impairs the controllability of the threshold voltage Vth of the MIS transistor and lowers the mobility, and several methods have been proposed to remove it.
その一つとして９００℃程度の高温アニールを行なう方
法があるが電極形成後では難しい場合がある。又４５０
℃程度の温度の、Ｎｏ−Ｈｏ雰囲気中で３紛程度アニー
ルする方法があるが、特にＮｏ、東ゝ（金属−窒化膜一
酸化膜−半導体）構造では不充分である。さらに他の１
つとしては米国特許第４０１３４８５号に開示されるよ
うに基板を高周波電界の印加されたプラズマ雰囲気中に
設置する方法であるが、プラズマを発生させるために減
圧しなければならないとか、プラズマが基板にダメージ
を与えるといつた欠点がある。One method is to perform high-temperature annealing at about 900° C., but this may be difficult after electrode formation. Also 450
There is a method of annealing approximately 3 layers in a No--Ho atmosphere at a temperature of about 0.degree. C., but this is insufficient, especially for No. Yet another one
One method, as disclosed in U.S. Pat. No. 4,013,485, is to place the substrate in a plasma atmosphere to which a high-frequency electric field is applied. It has the drawback of causing damage.
本発明はこのような点に鑑みて成されたもので、その目
的は従来の欠点を解決し常圧下で容易に界面準位を減少
させることにあり、本発明では絶縁膜が被着された半導
体基板を高周波電界中に配置し、該半導体基板に紫外線
を照射すると共に該半導体基板を加熱することを特徴と
する。The present invention has been made in view of these points, and its purpose is to solve the conventional drawbacks and easily reduce the interface states under normal pressure. The method is characterized in that a semiconductor substrate is placed in a high-frequency electric field, the semiconductor substrate is irradiated with ultraviolet rays, and the semiconductor substrate is heated.
以下図面を参照して本発明を説明する。図は本発明の一
実施例を説明するための図である。The present invention will be explained below with reference to the drawings. The figure is a diagram for explaining one embodiment of the present invention.
図のように半導体基板１を発振器５と電極２、３によつ
て作られる１３．５酪椙ｚの電界中に配置すると共に４
００Ｗの紫外線ランプを用い紫外線および赤外線４を基
板に対して照射する。尚、この際の電界強度はＩＯＫＶ
ＩＷＵ！を）基板温度１４５０℃、Ｎｏ−Ｈｏ雰囲気中
であつた。As shown in the figure, the semiconductor substrate 1 is placed in an electric field of 13.5 degrees created by an oscillator 5 and electrodes 2 and 3, and
The substrate is irradiated with ultraviolet rays and infrared rays 4 using a 00W ultraviolet lamp. In addition, the electric field strength at this time is IOKV
IWU! ) The substrate temperature was 1450° C. in a No-Ho atmosphere.
このような実施例においてＭＯＳ（Ｍｅｔａｌ一Ｏｘｉ
ｄｅ−Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）ダイオードは２Ω
−ａＰ型シリコン基板の（１００）面上にＳｉＯ２を１
０００Λ形成させ、次いで電子ビーム蒸着でアルミニウ
ム・電極を形成したものについてフラットバンド電圧Ｖ
ＦＢを測定した。その結果上記実施例においては、初期
状態のＶＦＢ＝−１．６Ｖであつたものがこの実施例を
適用することによりＶＦＢ■−Ｏ、７Ｖとなつたが、従
来の単に４５０℃のＨ２−Ｎ２雰囲気中でアニールを行
なつたものは−１．０Ｖにとどまつた。また紫外線を同
時に加えても同様の結果であつた。この結果から、本発
明が従来のアニールに比らべ界面準位の減少に効果を奏
することが確かめられた。In such embodiments, MOS (Metal-Oxi)
de-Semiconductor) diode is 2Ω
-1 SiO2 on the (100) plane of the aP type silicon substrate
000Λ, and then formed an aluminum electrode by electron beam evaporation, the flat band voltage V
FB was measured. As a result, in the above example, VFB = -1.6V in the initial state became VFB - O, 7V by applying this example, but compared to the conventional case where VFB = -1. Those annealed in an atmosphere remained at -1.0V. Similar results were obtained even when ultraviolet rays were added at the same time. From this result, it was confirmed that the present invention is more effective in reducing interface states than conventional annealing.
尚、上記実施例では基板温度を４５０℃としたが、本発
明はこれに限らずジャンクションの破壊が起こらない５
００′Ｃ以下２００゜Ｃ以上の適当な基板温度となるよ
うに加熱することによつて実際的な効果が得られる。In the above embodiment, the substrate temperature was set at 450°C, but the present invention is not limited to this.
Practical effects can be obtained by heating the substrate to an appropriate temperature of 00'C or lower and 200C or higher.
以上述べたように本発明によれば従来例に比らべ減圧す
ることなく又プラズマによるダメージの心配もなく常圧
で界面準位をより減少させることができるので製造装置
が簡単になりしかもＶｔｈのより小さな■Ｓトランジス
タを製造することができる。As described above, according to the present invention, compared to the conventional example, the interface states can be further reduced at normal pressure without reducing the pressure and without worrying about damage caused by plasma, which simplifies the manufacturing equipment. It is possible to manufacture smaller ■S transistors.
図は本発明の一実施例を説明するための図てある。
図において、１は半導体基板、２，３は電極、４は紫外
線と赤外線、５は高周波発振器を示す。The figure is a diagram for explaining one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 and 3 are electrodes, 4 is an ultraviolet ray and an infrared ray, and 5 is a high frequency oscillator.
Claims (1)
置し、該半導体基板に紫外線を照射すると共に該半導体
基板を加熱することを特徴とする半導体装置の製造方法
。1. A method for manufacturing a semiconductor device, which comprises placing a semiconductor substrate coated with an insulating film in a high-frequency electric field, irradiating the semiconductor substrate with ultraviolet rays, and heating the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16163978A JPS6041849B2 (en) | 1978-12-23 | 1978-12-23 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16163978A JPS6041849B2 (en) | 1978-12-23 | 1978-12-23 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5586123A JPS5586123A (en) | 1980-06-28 |
| JPS6041849B2 true JPS6041849B2 (en) | 1985-09-19 |
Family
ID=15739003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16163978A Expired JPS6041849B2 (en) | 1978-12-23 | 1978-12-23 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041849B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63138741A (en) * | 1986-12-01 | 1988-06-10 | Nippon Telegr & Teleph Corp <Ntt> | Annealing device for compound semiconductor substrate |
| JPH07321061A (en) * | 1994-10-03 | 1995-12-08 | Sony Corp | Manufacture of semiconductor device |
-
1978
- 1978-12-23 JP JP16163978A patent/JPS6041849B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5586123A (en) | 1980-06-28 |
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