KR100267491B1 - Method for pre-treatment of silicon substrate - Google Patents

Method for pre-treatment of silicon substrate Download PDF

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Publication number
KR100267491B1
KR100267491B1 KR1019970030022A KR19970030022A KR100267491B1 KR 100267491 B1 KR100267491 B1 KR 100267491B1 KR 1019970030022 A KR1019970030022 A KR 1019970030022A KR 19970030022 A KR19970030022 A KR 19970030022A KR 100267491 B1 KR100267491 B1 KR 100267491B1
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silicon substrate
gate oxide
oxide film
hydrogen
roughness
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KR1019970030022A
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Korean (ko)
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KR19990005804A (en
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우선웅
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

PURPOSE: A method for pretreating a silicon substrate is provided to increase carrier mobility in a channel under a gate oxide layer by reducing the roughness of the surface of the silicon substrate, and to prevent an abnormal growth of the gate oxide layer formed in a subsequent process by forming a hydrogen passivation layer. CONSTITUTION: A silicon substrate is annealed in a hydrogen atmosphere for more than an hour and at a temperature scope from 600 deg.C to 1000 deg.C, so that the roughness of the surface of the silicon substrate is reduced while a hydrogen passivation layer is formed.

Description

실리콘기판의 전처리방법{Method for pre-treatment of silicon substrate}Method for pre-treatment of silicon substrate

본 발명은 실리콘기판의 전처리방법에 관한 것으로서, 특히 실리콘기판 상에 게이트산화막을 형성하는 경우에 그 표면거칠기를 감소시키기 위해 행해지는 실리콘기판의 전처리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for pretreatment of a silicon substrate, and more particularly to a method for pretreatment of a silicon substrate to reduce the surface roughness when forming a gate oxide film on the silicon substrate.

실리콘기판을 사용하는 반도체소자의 제조공정 중 게이트산화막 형성 전에는 실리콘기판의 표면에 필연적으로 발생하는 자연산화막(native oxide)을 제거하기 위해 전처리공정을 거치게 되어 있다. 그러나, 자연산화막을 제거하게 되면, 도1에 도시된 바와 같이, 4가의 공유결합을 이루는 실리콘이 그 표면에서는 결합을 이루지 못하는 실리콘원자의 본드(10), 즉 댕글링본드를 가지게 되므로, 실리콘기판의 표면거칠기는 0.12∼0.15㎚의 RMS(Root Mean Square)값을 가지게 된다. 이러한 거칠기를 가진 실리콘표면 위에서 열확산에 의해 성장하는 게이트산화막은 많은 트랩사이트(trap site)를 형성하게 될 뿐 아니라, 상기 댕글링본드에서는 게이트산화막이 급속한 이상성장을 하게 되어 게이트산화막의 막질에도 나쁜 영향을 미치게 된다. 이에 따라, 궁극적으로 소자의 특성도 열화되게 된다.Before the gate oxide film is formed during the manufacturing process of the semiconductor device using the silicon substrate, a pretreatment process is performed to remove a native oxide that inevitably occurs on the surface of the silicon substrate. However, when the natural oxide film is removed, as shown in FIG. 1, since the tetravalent covalent silicon has a bond 10 of silicon atoms, i.e., a dangling bond, which cannot form a bond on its surface, a silicon substrate The surface roughness of has a root mean square (RMS) value of 0.12 to 0.15 nm. The gate oxide film grown by thermal diffusion on the silicon surface having such roughness not only forms many trap sites, but also causes abnormal abnormal growth of the gate oxide film in the dangling bonds due to the rapid abnormal growth. Get mad. Accordingly, ultimately, the characteristics of the device also deteriorate.

상기한 문제점을 해결하기 위한 본 발명의 목적은 실리콘기판 상에 게이트산화막을 형성하는 경우에 그 표면거칠기를 감소시키기 위한 실리콘기판의 전처리방법을 제공하는 데 있다.An object of the present invention for solving the above problems is to provide a silicon substrate pretreatment method for reducing the surface roughness when forming a gate oxide film on the silicon substrate.

본 발명의 다른 목적은 실리콘기판 상에 게이트산화막을 형성하는 경우에 미결합된 실리콘원자의 본드(dangling bond)를 없애는 수소보호막을 형성시켜 후속하여 형성되는 게이트산화막의 이상성장을 방지하는 실리콘기판의 전처리방법을 제공하는 데 있다.Another object of the present invention is to form a hydrogen protective film that removes unbonded silicon atoms from bonding when a gate oxide film is formed on a silicon substrate, thereby preventing abnormal growth of the gate oxide film formed subsequently. To provide a pretreatment method.

도 1은 종래 기술에 의한 실리콘기판의 전처리방법을 적용한 후의 실리콘기판 표면의 확대단면도,1 is an enlarged cross-sectional view of a silicon substrate surface after applying the silicon substrate pretreatment method according to the prior art;

도 2는 본 발명의 실시예에 의한 실리콘기판의 전처리방법을 적용한 후의 실리콘기판 표면의 확대단면도이다.2 is an enlarged cross-sectional view of a silicon substrate surface after applying the silicon substrate pretreatment method according to the embodiment of the present invention.

* 도면의 주요부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *

Si … 실리콘원자Si… Silicon atom

H … 수소원자H… Hydrogen atom

10 … 댕글링본드10... Dangling Bond

상기한 목적들을 달성하기 위한 본 발명의 실리콘기판의 전처리방법은, 실리콘기판 상에 게이트산화막을 형성하기 위한 실리콘기판의 전처리방법에 있어서, 상기 실리콘기판을 수소분위기 내에서 어닐링하여 상기 실리콘기판 표면의 거칠기를 감소시키는 동시에 보호하는 수소보호막을 형성하는 것을 특징으로 한다.In order to achieve the above objects, a silicon substrate pretreatment method includes a silicon substrate pretreatment method for forming a gate oxide film on a silicon substrate, wherein the silicon substrate is annealed in a hydrogen atmosphere to form a surface of the silicon substrate. It is characterized by forming a hydrogen protective film which reduces and reduces roughness.

본 발명에 있어서, 상기 어닐링은 600∼1000℃의 온도에서 1시간 이상 실행되는 것이 바람직하다.In the present invention, the annealing is preferably carried out for at least 1 hour at a temperature of 600 ~ 1000 ℃.

이 때, 상기 어닐링에 의해 수소보호막을 형성하기 전에 상기 실리콘기판을 세정하는 단계를 더 구비하는 것을 더욱 바람직하며, 상기 세정단계는 희석된 불산용액을 이용하여 자연산화막을 제거하는 공정인 것이 더욱 바람직하다.At this time, it is more preferable to further comprise the step of cleaning the silicon substrate before forming the hydrogen protective film by the annealing, the cleaning step is more preferably a step of removing the natural oxide film using a diluted hydrofluoric acid solution. Do.

이하, 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명한다. 또한, 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다.Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention. In addition, this embodiment does not limit the scope of the present invention, but is presented by way of example only.

도 2는 본 발명의 실시예에 의한 실리콘기판의 전처리방법을 적용한 후의 실리콘기판 표면의 확대단면도이다.2 is an enlarged cross-sectional view of a silicon substrate surface after applying the silicon substrate pretreatment method according to the embodiment of the present invention.

상기 전처리방법을 적용하기에 앞서, 실리콘기판 상에 필연적으로 발생하는 자연산화막(∼20Å)을 제거하기 위하여, 희석된 불산용액을 이용하여 실리콘기판을 세정한다. 보통 불산용액은 순수:불산=50∼100:1 정도의 것을 사용한다. 이 단계가 완료되면, 실리콘기판은 도1에 도시한 바와 같은 표면거칠기를 갖게 된다. 이와 같은 실리콘기판을 수소분위기 내에서 850℃의 온도에서 90분 정도 어닐링하면, 수소원자(H)에 의해 종단처리된 실리콘(hydrogen terminated silicon)기판 표면을 얻게된다. 이 수소원자는 실리콘기판 표면 전체에 형성되는 수소보호막의 역할을 행할 뿐 아니라, 수소원자 자체가 작은 원자반경을 가지고 있으므로, 실리콘(Si)을 비롯한 각종 물질에 침입형으로 침투할 경우, 실리콘기판의 실리콘원자 사이에 침입하여 보다 평탄한 표면거칠기(약 0.08㎚의 RMS값)를 가지게 한다.Prior to applying the pretreatment method, the silicon substrate is cleaned using a dilute hydrofluoric acid solution in order to remove a natural oxide film (˜20 μs) inevitably generated on the silicon substrate. Usually, hydrofluoric acid solution is used pure water: hydrofluoric acid = 50 ~ 100: 1. When this step is completed, the silicon substrate has a surface roughness as shown in FIG. When the silicon substrate is annealed at a temperature of 850 ° C. for about 90 minutes in a hydrogen atmosphere, a surface of a hydrogen terminated silicon substrate terminated by a hydrogen atom (H) is obtained. This hydrogen atom not only acts as a hydrogen protective film formed on the entire surface of the silicon substrate, but also has a small atomic radius. Therefore, when the hydrogen atom penetrates into various materials including silicon (Si) in an invasive manner, It penetrates between silicon atoms and has a flatter surface roughness (RMS value of about 0.08 nm).

또한, 실리콘원자가 수소원자에 의해 종단처리되면, 반응성이 낮아져 후속하는 게이트산화막의 성장을 위한 공정에 있어서의 지연 중, 또는 공정온도에 도달하기 위한 온도상승(ramp-up) 시의 산화막의 이상성장이 방지되므로, 실리콘표면의 보호막(passivation layer) 역할도 수행하게 된다.In addition, when the silicon atoms are terminated by hydrogen atoms, the reactivity becomes low and abnormal growth of the oxide film during the delay in the process for the growth of the subsequent gate oxide film or when the temperature rises to reach the process temperature is achieved. Since this is prevented, it also serves as a passivation layer on the silicon surface.

본 발명에 의하면, 실리콘기판 표면의 거칠기가 감소되므로, 게이트산화막 하부의 채널에서의 캐리어 이동도(carrier mobility)가 증가하여 소자의 고속화가 가능해진다.According to the present invention, since the roughness of the surface of the silicon substrate is reduced, carrier mobility in the channel under the gate oxide film is increased, thereby making it possible to speed up the device.

또한, 수소보호막을 형성시켜 후속하여 형성되는 게이트산화막의 이상성장을 방지하므로, 우수한 트랜지스터 특성을 갖게 할 수 있다.In addition, since a hydrogen protective film is formed to prevent abnormal growth of a subsequently formed gate oxide film, excellent transistor characteristics can be obtained.

Claims (1)

실리콘기판 상에 게이트산화막을 형성하기 위한 실리콘기판의 전처리방법에 있어서,In the silicon substrate pretreatment method for forming a gate oxide film on the silicon substrate, 상기 실리콘기판을 수소분위기 내에서 600∼1000℃의 온도에서 1시간 이상 어닐링하여 상기 실리콘기판 표면의 거칠기를 감소시키는 동시에 보호하는 수소보호막을 형성하는 것을 특징으로 하는 실리콘기판의 전처리방법.And annealing the silicon substrate at a temperature of 600 to 1000 ° C. in a hydrogen atmosphere for at least 1 hour to form a hydrogen protective film that reduces and protects the roughness of the surface of the silicon substrate.
KR1019970030022A 1997-06-30 1997-06-30 Method for pre-treatment of silicon substrate KR100267491B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100411194C (en) * 2003-06-25 2008-08-13 三星Sdi株式会社 Thin film transistor and plane display device
US10153170B2 (en) 2016-06-10 2018-12-11 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226315A (en) * 1992-02-10 1993-09-03 Sharp Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226315A (en) * 1992-02-10 1993-09-03 Sharp Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100411194C (en) * 2003-06-25 2008-08-13 三星Sdi株式会社 Thin film transistor and plane display device
US10153170B2 (en) 2016-06-10 2018-12-11 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device

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