JPS624316A - Annealing of semiconductor device - Google Patents

Annealing of semiconductor device

Info

Publication number
JPS624316A
JPS624316A JP60143249A JP14324985A JPS624316A JP S624316 A JPS624316 A JP S624316A JP 60143249 A JP60143249 A JP 60143249A JP 14324985 A JP14324985 A JP 14324985A JP S624316 A JPS624316 A JP S624316A
Authority
JP
Japan
Prior art keywords
semiconductor
oxide film
silicon
energy
absorbed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60143249A
Other languages
Japanese (ja)
Inventor
Masayoshi Kitamura
北村 昌良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP60143249A priority Critical patent/JPS624316A/en
Publication of JPS624316A publication Critical patent/JPS624316A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide an annealing method which does not have influence upon the previously formed wiring s by a method wherein light which has energy smaller than the energy of a forbiddedn band of a semiconductor is applied to the back plane of the semiconductor and absorbed by a defective part and thermal annealing is carried out. CONSTITUTION:Infrared rays, which have smaller energy then the energy of a forbidden band of silicon, are applied to the surface 1a opposite to the oxide film 8 side of a semiconductor substrate 1. As a result, the infrared rays transmit through the silicon substrate 1, an epitaxial growth layer 2, a drain region 3 and a source region 4, and are absorbed to the boundary between the layer 2 or regions 3 and 4 and the oxide film 8. Therefore, heat is generated at the parts where the infrared rays are absorbed and the crystal defect parts of silicon at the boundary are efficiently heated and annealed so that the defects are removed. In such process, aluminum wirings 5 and 6 and the oxide film 8 are not influenced at all.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体の一方の面に発生した結晶欠陥を除去
するためのアニール方法に関゛する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an annealing method for removing crystal defects generated on one surface of a semiconductor.

〔従来技術〕[Prior art]

MOSタイプの半導体装置の製造途中では、シリコン(
Si)とその上面に形成される酸化シリコン(S i 
Ox )との界面におけるシリコン結晶に、イオン、電
子、X線、γ線等の照射によって結晶欠陥が誘起され、
デバイス特性を損なうことが多い。
During the manufacturing of MOS type semiconductor devices, silicon (
Si) and silicon oxide (Si
Crystal defects are induced in the silicon crystal at the interface with Ox) by irradiation with ions, electrons, X-rays, γ-rays, etc.
This often impairs device characteristics.

そこで従来では、その欠陥の除去のために、その部分に
熱を加える熱的アニール処理を施しているが、これは通
常はTOO℃程度以上の温度で行われる。しかし、アル
ミニウム配線の後では、そのアルミニウムの融点との関
係から、570℃以上に昇温させることはできず、低温
での処理が望まれていた。
Therefore, conventionally, in order to remove these defects, a thermal annealing treatment is performed to apply heat to the defective portion, but this is usually performed at a temperature of approximately TOO° C. or higher. However, after the aluminum wiring, it is impossible to raise the temperature above 570° C. due to the relationship with the melting point of aluminum, and a low-temperature treatment has been desired.

このために、シリコン酸化膜の外側から赤外線を照射し
て短時間にアニールすることが提案されているが、これ
は、■シリコン酸化物中に吸収されて深くは赤外線が浸
入せずアニール効果が薄いこと、及び■金属配線の下側
−は赤外線が通らず、その部分に対して効果がない等の
欠点があった。
For this purpose, it has been proposed to irradiate infrared rays from the outside of the silicon oxide film to anneal it in a short period of time. There were drawbacks such as being thin, and (1) infrared rays do not pass through the underside of the metal wiring, making it ineffective for that area.

〔発明の目的〕[Purpose of the invention]

本発明はこのような点に鑑みてなされたものであり、そ
の目的は、酸化膜や既に配線されているアルミニウム配
線の影響を受けることのないアニール方法を提供するこ
とである。
The present invention has been made in view of these points, and its purpose is to provide an annealing method that is not affected by the oxide film or the aluminum wiring that has already been wired.

〔発明の構成] このために本発明では、半導体の一方の面の側の結晶欠
陥を除去するアニール方法において、該半導体の禁制帯
幅よりもエネルギーの小さい光を、該半導体の上記面と
反対側の面から照射して、半導体では吸収されずに透過
させて上記欠陥部分に吸収させ、上記欠陥部分を加熱ア
ニールするようにした。
[Structure of the Invention] For this purpose, in the present invention, in an annealing method for removing crystal defects on one surface of a semiconductor, light having an energy smaller than the forbidden band width of the semiconductor is directed to the opposite side of the surface of the semiconductor. It is irradiated from the side surface, and is transmitted without being absorbed by the semiconductor, and is absorbed by the defective portion, thereby heating and annealing the defective portion.

〔実施例〕〔Example〕

以下、本発明の実施例について説明する。図はnチャン
ネルのエンハンスメント型のMO5I−ランジスタの例
を示すものである。1はp型シリコンの半導体基板、2
はn型のエピタキシャル成長層、3はp型のドレイン領
域、4はp型のソース領域、5はアルミニウム配線でな
るドレイン電極、6は同様のソース電極、7はゲート電
極、8はシリコン酸化膜(S i Ox )である。
Examples of the present invention will be described below. The figure shows an example of an n-channel enhancement type MO5I transistor. 1 is a p-type silicon semiconductor substrate, 2
is an n-type epitaxial growth layer, 3 is a p-type drain region, 4 is a p-type source region, 5 is a drain electrode made of aluminum wiring, 6 is a similar source electrode, 7 is a gate electrode, and 8 is a silicon oxide film ( S i Ox ).

前記した結晶欠陥は、酸化膜8とエピタキシャル成長層
2やドレイン領域3、ソース領域で発生し易い。
The crystal defects described above are likely to occur in the oxide film 8, epitaxial growth layer 2, drain region 3, and source region.

そこで本発明では、シリコンの禁制帯幅(1,1eV)
のエネルギー(波長が約1 、200nm)よりもエネ
ルギーの小さい赤外線光(1,500nm程度の波長)
を半導体基板1の酸化膜8側と反対側の面1a(シリコ
ンウェハの裏面)から照射するようにした。
Therefore, in the present invention, the forbidden band width of silicon (1.1 eV)
Infrared light (wavelength of about 1,500 nm) has lower energy than the energy of (wavelength of about 1,200 nm)
is irradiated from the surface 1a of the semiconductor substrate 1 opposite to the oxide film 8 side (the back surface of the silicon wafer).

この結果、その赤外線光は、シリコンで成る基板1、エ
ピタキシャル成長層2、ドレイン領域3及びソース領域
4内を通過して、酸化膜8との界面で吸収されるように
なる。よって、その吸収部分で発熱が起り、その界面の
シリコン結晶欠陥部分が効率よく加熱され、アニールさ
れて欠陥が除去されるようになる。このとき、アルミニ
ウム配線(電極5.6)や酸化膜8による影響は全くう
けない。
As a result, the infrared light passes through the substrate 1 made of silicon, the epitaxial growth layer 2, the drain region 3, and the source region 4, and is absorbed at the interface with the oxide film 8. Therefore, heat generation occurs in the absorbing portion, and the silicon crystal defect portion at the interface is efficiently heated, annealed, and the defect is removed. At this time, there is no influence from the aluminum wiring (electrodes 5, 6) or the oxide film 8.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、ウェハ裏面からの光照射
によっているため、アルミニウム配線終了後であっても
、酸化膜との界面を効率よくアニールすることができ、
その部分に発生している結晶欠陥を除去することが可能
となる。
As described above, according to the present invention, since light is irradiated from the back side of the wafer, the interface with the oxide film can be efficiently annealed even after the aluminum wiring is completed.
It becomes possible to remove crystal defects occurring in that part.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の説明用のMO3!−ランジスタの断面図で
ある。 1・・・シリコンめ半導体基板、2・・・エピタキシャ
ル成長層、3・・・ドレイン領域、4・・・ソース領域
、5・・・ドレイン電極、6・・・ソース電極、7・・
・ゲート電極、8・・・シリ・コン酸化膜。 特許出願人 新日本無線株式会社 代 理 人 弁理士  長尾常明 SG    D 、1、夕[必艮g、y
The figure is MO3 for explaining the present invention! - a sectional view of a transistor; DESCRIPTION OF SYMBOLS 1... Silicon semiconductor substrate, 2... Epitaxial growth layer, 3... Drain region, 4... Source region, 5... Drain electrode, 6... Source electrode, 7...
- Gate electrode, 8... silicon oxide film. Patent applicant New Japan Radio Co., Ltd. Agent Patent attorney Tsuneaki Nagao SG D, 1, evening

Claims (1)

【特許請求の範囲】[Claims] (1)、半導体の一方の面の側の結晶欠陥を除去するア
ニール方法において、該半導体の禁制帯幅よりもエネル
ギーの小さい光を、該半導体の上記面と反対側の面から
照射して、上記欠陥部分に吸収させ、上記欠陥部分を加
熱アニールするようにしたことを特徴とする半導体装置
のアニール方法。
(1) In an annealing method for removing crystal defects on one side of a semiconductor, irradiating light with energy smaller than the forbidden band width of the semiconductor from the side opposite to the above-mentioned side of the semiconductor, A method for annealing a semiconductor device, characterized in that the defective portion is absorbed by the defective portion and the defective portion is heated and annealed.
JP60143249A 1985-06-29 1985-06-29 Annealing of semiconductor device Pending JPS624316A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60143249A JPS624316A (en) 1985-06-29 1985-06-29 Annealing of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60143249A JPS624316A (en) 1985-06-29 1985-06-29 Annealing of semiconductor device

Publications (1)

Publication Number Publication Date
JPS624316A true JPS624316A (en) 1987-01-10

Family

ID=15334353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60143249A Pending JPS624316A (en) 1985-06-29 1985-06-29 Annealing of semiconductor device

Country Status (1)

Country Link
JP (1) JPS624316A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289546A (en) * 2001-03-27 2002-10-04 Denso Corp Device and method for producing silicon carbide semiconductor
JP2005183604A (en) * 2003-12-18 2005-07-07 Semiconductor Leading Edge Technologies Inc Method for heat treatment of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289546A (en) * 2001-03-27 2002-10-04 Denso Corp Device and method for producing silicon carbide semiconductor
JP2005183604A (en) * 2003-12-18 2005-07-07 Semiconductor Leading Edge Technologies Inc Method for heat treatment of semiconductor device

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