JPS633447B2 - - Google Patents

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Publication number
JPS633447B2
JPS633447B2 JP54089917A JP8991779A JPS633447B2 JP S633447 B2 JPS633447 B2 JP S633447B2 JP 54089917 A JP54089917 A JP 54089917A JP 8991779 A JP8991779 A JP 8991779A JP S633447 B2 JPS633447 B2 JP S633447B2
Authority
JP
Japan
Prior art keywords
junction
layer
mask
semiconductor substrate
deep
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54089917A
Other languages
Japanese (ja)
Other versions
JPS5615035A (en
Inventor
Mitsunori Ketsusako
Haruo Ito
Tadashi Saito
Nobuo Nakamura
Takashi Tokuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP8991779A priority Critical patent/JPS5615035A/en
Publication of JPS5615035A publication Critical patent/JPS5615035A/en
Publication of JPS633447B2 publication Critical patent/JPS633447B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 本発明は基板表面に浅いPN接合を有する半導
体基板表面の局所部に高エネルギーのレーザ光を
投射し、局所部を加熱すると共に該局所部に存在
する不純物を半導体基板内に拡散させて上記局所
部に対応する部分に深いPN接合部を形成する半
導体装置の製造方法に関している。
Detailed Description of the Invention The present invention projects a high-energy laser beam onto a localized portion of the surface of a semiconductor substrate having a shallow PN junction on the substrate surface, heats the localized portion, and removes impurities present in the localized portion of the semiconductor substrate. The present invention relates to a method of manufacturing a semiconductor device in which a deep PN junction is formed in a portion corresponding to the local portion by diffusion inward.

半導体基板表面に浅いPN接合、例えば表面か
らの深さ0.1μm〜0.2μm程度の浅いPN接合の形
成は、太陽電池、高周波トランジスタ等で必要と
される。この浅いPN接合の形成技術は不純物の
塗布拡散法、不純物のイオン打込み法等いくつか
の製法が開発されている。この浅いPN接合で特
に問題になるのは電極形成時のPN接合の破壊で
ある。即ち、0.1μm〜0.2μm程度の浅いP型ある
いはN型半導体層に電極金属を蒸着で形成する時
に半導体層と電極金属層との界面で溶融、合金化
が起り、その結果、合金層によつて、浅いPN接
合が破壊される。
Formation of a shallow PN junction on the surface of a semiconductor substrate, for example, a shallow PN junction with a depth of about 0.1 μm to 0.2 μm from the surface, is required for solar cells, high frequency transistors, and the like. Several methods have been developed to form this shallow PN junction, including an impurity coating and diffusion method and an impurity ion implantation method. A particular problem with this shallow PN junction is destruction of the PN junction during electrode formation. That is, when an electrode metal is formed by vapor deposition on a shallow P-type or N-type semiconductor layer of about 0.1 μm to 0.2 μm, melting and alloying occur at the interface between the semiconductor layer and the electrode metal layer, and as a result, the alloy layer As a result, the shallow PN junction is destroyed.

従来、上記浅いPN接合の問題点を解決するた
めには、浅いP(又はN)型層の一部に不純物の
選択拡散法、イオン打込み法等で深いP(又はN)
型の層を形成し、即ち、上記浅いPN接合の一部
に深いPN接合を形成し、この深いPN接合部に
電極を形成して問題の解決を計つている。
Conventionally, in order to solve the problems of shallow PN junctions mentioned above, deep P (or N) junctions were formed by selectively diffusing impurities, ion implantation, etc. into a part of the shallow P (or N) type layer.
The problem is solved by forming a mold layer, that is, forming a deep PN junction in a part of the shallow PN junction, and forming an electrode in this deep PN junction.

しかし、上記従来方法では、例えば、不純物の
選択拡散の場合にはSiO2膜の形成工程、ホトレ
ジ加工によるマスクの形成工程、不純物ガス雰囲
気中に於ける拡散熱処理工程、イオン打込み法の
場合には打込みの際のマスク合せ工程、不純物イ
オンの打込み後打込みイオンの活性化のための熱
処理工程等の処理が必要である。これ等の処理工
程はそれぞれ長時間を要し、又精密加工であるた
めに高度の製造技術が必要とされる。特に、深い
PN接合部に電極層を形成するのに、イオン打込
み法を利用した場合、イオン打込みで形成した深
いPN接合部の判別が難かしく、電極金属層形成
のための蒸着マスクの位置合せが困難で、電極用
蒸着金属層が深いPN接合部からずれ、浅いPN
接合部上に伸びることがしばしば生じる。これは
前述した通り、浅いPN接合を破壊し、製造歩留
を下げることになる。
However, in the above conventional method, for example, in the case of selective diffusion of impurities, there is a SiO 2 film formation process, a mask formation process by photoresist processing, a diffusion heat treatment process in an impurity gas atmosphere, and in the case of ion implantation, Processes such as a mask alignment process during implantation and a heat treatment process for activating the implanted ions after impurity ion implantation are required. Each of these processing steps takes a long time, and since they are precision processing, advanced manufacturing technology is required. especially deep
When ion implantation is used to form an electrode layer on a PN junction, it is difficult to distinguish the deep PN junction formed by ion implantation, and it is difficult to align the vapor deposition mask for forming the electrode metal layer. , the deposited metal layer for the electrode is shifted from the deep PN junction, and the shallow PN
Stretching over the joints often occurs. As mentioned above, this destroys the shallow PN junction and lowers the manufacturing yield.

以上述べた様に、従来方法では作業工程が多い
のと、処理に相当時間が掛ることから生産性が悪
く、しかも、歩留が低い、その結果、製品単価を
引き上げる結果となつている。
As mentioned above, the conventional method involves many work steps and takes a considerable amount of time, resulting in poor productivity and low yield, resulting in an increase in the product unit price.

そこで、本発明の目的は浅いPN接合部の一部
に深いPN接合を短時間に、しかも容易に形成す
る半導体装置の製造方法を提案するにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to propose a method for manufacturing a semiconductor device that easily forms a deep PN junction in a portion of a shallow PN junction in a short time.

本発明の他の目的は浅いPN接合の一部に深い
PN接合部を短時間に、しかも容易に形成し、更
に上記深いPN接合表面部のみに正確に電極用金
属層を設ける半導体装置の製造方法を提案するに
ある。
Another object of the present invention is to provide a deep
The object of the present invention is to propose a method for manufacturing a semiconductor device in which a PN junction can be easily formed in a short time, and furthermore, an electrode metal layer can be precisely provided only on the deep PN junction surface.

最近、半導体基板表面に不純物をイオン打込み
法により所定深さ打込んだ後、基板表面に高エネ
ルギーのレーザ光を、短時間(1〜2J/cm2、数
nsec)投射すると打込まれた不純物イオンが電気
的に活性化し、半導体基板に対し導電型決定不純
物として作用する様になる旨の報告がなされた。
(G.A.Kachurin、V.A.Bogatyriov、S.I.
Romanov and L.S.Smirnov、Proc.of Ion
Implantation of Semicon.、
p.445Corolado1976) この報告された技術は、イオン打込み後の半導
体基板のアニール処理をレーザ光投射により短時
間に済ませることができる等の利点から生産性の
向上対策として有望視され始めた。
Recently, after implanting impurities into the surface of a semiconductor substrate to a predetermined depth using the ion implantation method, high-energy laser light is applied to the surface of the substrate for a short period of time (1 to 2 J/cm 2 , several
It has been reported that when the impurity ions are projected (nsec), the implanted impurity ions become electrically activated and act as conductivity type determining impurities on the semiconductor substrate.
(GA Kachurin, VA Bogatyriov, SI
Romanov and LSSmirnov, Proc. of Ion
Implantation of Semicon.
(p. 445 Colorado 1976) This reported technology began to be seen as a promising measure for improving productivity due to its advantages such as being able to complete annealing of a semiconductor substrate after ion implantation in a short time by laser beam projection.

本発明者等は上記事実を更に研究する段階で、
次の事実を確認した。半導体表面領域に不純物ド
ープ層を形成後、このドープ層に高エネルギーの
レーザ光を短時間投射すると、ドープ層中の不純
物が半導体基板内に拡散し、ドープ層と半導体基
板との界面にPN接合が存在しているとすれば、
上記PN接合が高エネルギーレーザ光の投射によ
り基板内に更に深く進む事実である。この場合、
初期の不純物ドープ層の形成は不純物のイオン打
込み法に限らず、不純物の熱拡散法等でも差が認
められない。
The inventors are at the stage of further researching the above facts,
The following facts were confirmed. After forming an impurity-doped layer on the semiconductor surface region, if a high-energy laser beam is irradiated onto this doped layer for a short time, the impurities in the doped layer will diffuse into the semiconductor substrate, forming a PN junction at the interface between the doped layer and the semiconductor substrate. If there exists,
This is the fact that the above-mentioned PN junction advances deeper into the substrate by the projection of high-energy laser light. in this case,
The initial impurity-doped layer formation is not limited to impurity ion implantation methods, but there is no difference between impurity thermal diffusion methods and the like.

上記事実が確認できるのは初期ドープ層が浅
い、例えば深さ0.1〜0.2μm程度の層であつて、
この層にレーザ光を投射すると0.3〜0.5μm程度
に深くすることができる。
The above fact can be confirmed when the initial doped layer is shallow, for example, a layer with a depth of about 0.1 to 0.2 μm,
When a laser beam is projected onto this layer, the depth can be increased to about 0.3 to 0.5 μm.

本発明は上記の事実に着目して発明されたもの
であつて、浅いPN接合の一部に深いPN接合部
を形成する半導体装置の製法及び形成した上記深
いPN接合部の表面に正確に電極金属を設ける半
導体装置の製法である。
The present invention has been invented focusing on the above-mentioned fact, and includes a method for manufacturing a semiconductor device in which a deep PN junction is formed in a part of a shallow PN junction, and an electrode is precisely placed on the surface of the formed deep PN junction. This is a method for manufacturing a semiconductor device in which metal is provided.

この発明は第1導電型の半導体基板表面の所望
表面領域に第2導電型の不純物の浅いドープ層を
形成し、上記半導体基板表面上に所定形状の窓を
有するマスクを設けた後、このマスクを介して第
2導電型イオンの打込みおよびレーザ光の照射を
行なつて、上記マスクの窓に露出する半導体基板
表面領域への第2導電型の不純物の導入および該
不純物の上記半導体基板内への深い拡散を行な
い、しかる後上記マスクを上記半導体基板表面に
固定したまま上記半導体基板表面に電極用金属を
蒸着し上記マスクの窓に露出する半導体基板表面
部分に電極用金属蒸着層を形成する半導体装置の
造方法である。
This invention involves forming a shallow doped layer of impurities of a second conductivity type in a desired surface region of the surface of a semiconductor substrate of a first conductivity type, and providing a mask having a window of a predetermined shape on the surface of the semiconductor substrate. implanting ions of a second conductivity type and irradiating laser light through the mask to introduce impurities of a second conductivity type into the semiconductor substrate surface region exposed in the window of the mask and introduce the impurities into the semiconductor substrate. After that, while the mask is fixed to the surface of the semiconductor substrate, an electrode metal is vapor-deposited on the surface of the semiconductor substrate, and an electrode metal vapor-deposited layer is formed on the surface portion of the semiconductor substrate exposed to the window of the mask. This is a method for manufacturing semiconductor devices.

この発明は上記の構成であるため次の効果を有
する。
Since the present invention has the above configuration, it has the following effects.

(1) レーザ光を光学的に又はマスクにより細いビ
ーム状にすることが容易で、この細いビーム状
レーザ光や使用することにより、浅いPN接合
の所望部分に深いPN接合を作ることが容易に
できる。
(1) It is easy to make a laser beam into a thin beam optically or using a mask, and by using this narrow beam laser beam, it is easy to create a deep PN junction in the desired part of a shallow PN junction. can.

(2) 使用するレーザ光の半導体基板への投射時間
はレーザ光の強度で多少変わるが、約数n
sec程度で、レーザ光投射時間は瞬時的処理時
間であり、それだけ製品の製造時間を短縮でき
る。
(2) The projection time of the laser beam used on the semiconductor substrate varies somewhat depending on the intensity of the laser beam, but it is approximately several n.
The laser beam projection time is about seconds, which is an instantaneous processing time, and the manufacturing time of the product can be shortened accordingly.

(3) レーザ光投射は上述の通り瞬間的加熱処理で
あり、従来の熱処理拡散法では不可避であつた
横方向の不純物拡散が生じることがなく、それ
だけ製品に対する半導体基板面積を小さく、あ
るいは高密度化を可能にする。
(3) As mentioned above, laser beam projection is an instantaneous heat treatment, which eliminates the lateral impurity diffusion that is unavoidable with conventional heat treatment diffusion methods, which reduces the area of the semiconductor substrate for the product or allows for high density. make it possible to

(4) イオン打込みおよびレーザ光投射の際使用し
たマスクをマスクと半導体基板表面との相対的
位置を移動せずに、その後の電極金属蒸着の際
のマスクに使用するため、深いPN接合部表面
に正確に電極金属層を形成でき、その結果、製
品の歩留を高めることができる。
(4) The mask used during ion implantation and laser beam projection can be used as a mask during subsequent electrode metal deposition without moving the relative position between the mask and the semiconductor substrate surface. The electrode metal layer can be formed accurately, and as a result, the yield of products can be increased.

本発明で使用される浅いPN接合、深いPN接
合の用語は相対的なものであるが、例えば、浅い
PN接合とは電極金属形成の際にPN接合が破壊
される程度の深さで、通常、Si基板の場合0.1〜
0.2μm程度の深さを云い、深いPN接合とは電極
金属形成によつてもPN接合が破壊されない深さ
で、通常、Si基板の場合0.3μm以上の深さを云
う。
Although the terms shallow PN junction and deep PN junction used in the present invention are relative, for example, shallow
A PN junction is a depth that is such that the PN junction is destroyed during electrode metal formation, and is usually 0.1 to 0.1 in the case of a Si substrate.
A deep PN junction is defined as a depth of about 0.2 μm, and a deep PN junction is a depth at which the PN junction is not destroyed even when electrode metal is formed, and in the case of a Si substrate, it is usually a depth of 0.3 μm or more.

本発明に於いて、半導体基板表面の不純物ドー
プ層はイオン打込みで不純物をドープしたままの
状態の他、イオン打込み後アニールした後の状
態、不純物を基板表面から拡散によりドープした
状態等を含んでいる。従つて、本発明で、不純物
ドープ層と云う場合半導体基板との界面にPN接
合が形成されている場合、PN接合が形成されて
いない場合が含まれる。
In the present invention, the impurity-doped layer on the surface of the semiconductor substrate includes a state in which impurities are doped by ion implantation, a state after annealing after ion implantation, a state in which impurities are doped by diffusion from the substrate surface, etc. There is. Therefore, in the present invention, when referring to an impurity-doped layer, a case where a PN junction is formed at the interface with a semiconductor substrate or a case where a PN junction is not formed is included.

本発明で、レーザ光投射により不純物ドープ層
の一部の不純物を半導体基板内に更に拡散させる
深さはレーザ光の強度と投射時間に関係するが、
所定の強度又は投射時間を越えると半導体基板が
熱的歪のために割れることがある。
In the present invention, the depth at which some impurities in the impurity doped layer are further diffused into the semiconductor substrate by laser beam projection is related to the intensity of the laser beam and the projection time.
If a predetermined intensity or exposure time is exceeded, the semiconductor substrate may crack due to thermal strain.

以下、本発明を本発明の実施例により更に説明
する。
Hereinafter, the present invention will be further explained with reference to Examples of the present invention.

第1図乃至第6図はSi基板表面に形成した浅い
PN接合の一部に深いPN接合を形成する実施例
の説明図である。比抵抗0.1〜10Ω・cmのP型Si
基板(第1図)の表面に100eVのエネルギーでリ
ンイオンを1×1015個/cm2濃度で打込み、不純物
ドープ層2(第1図)を形成する。不純物ドープ
層の厚さは0.1μmである。次にルビーレーザから
の強さ1.0J/cm2のレーザ光3(第2図)を不純物
ドープ層2の表面に20n sec投射する。このレー
ザ光3(第2図)の投射でSi基板表面に打込まれ
たリンイオンは電気的に活性化し、ドープ層2を
n型Si層4(第2図)とする。この層4の深さは
浅く、表面から0.1μmの深さである。
Figures 1 to 6 show shallow depths formed on the surface of a Si substrate.
FIG. 3 is an explanatory diagram of an example in which a deep PN junction is formed in a part of the PN junction. P-type Si with specific resistance 0.1~10Ω・cm
Phosphorus ions are implanted into the surface of the substrate (FIG. 1) at a concentration of 1×10 15 ions/cm 2 at an energy of 100 eV to form an impurity doped layer 2 (FIG. 1). The thickness of the impurity doped layer is 0.1 μm. Next, a laser beam 3 (FIG. 2) with an intensity of 1.0 J/cm 2 from a ruby laser is projected onto the surface of the impurity-doped layer 2 for 20 nsec. The phosphorus ions implanted into the surface of the Si substrate by the projection of this laser beam 3 (FIG. 2) are electrically activated, and the doped layer 2 becomes an n-type Si layer 4 (FIG. 2). The depth of this layer 4 is shallow, 0.1 μm from the surface.

次に、150μm×150μmの窓5(第3図)を有
する厚さ100μmのMoマスク6(第3図)を半導
体基板1の表面に載置する。しかる後、エネルギ
ーを2J/cm2に高めたレーザ光7(第4図)をSi基
板表面に投射する。基板表面は第4図から明らか
な様にマスクの窓5以外すべてMoマスク6で被
われているため、マスクの窓に露出するn型Si層
のみを高エネルギーレーザ光が投射する。強さ
2J/cm2の高エネルギーのレーザ光を約10n sec投
射するとn型Si層4(第4図)の内レーザ光によ
り投射された領域のリンが固体内拡散を起し、第
4図に示すように、基板内に深く入つた(0.3μ
m)n型層8(以後、深いPN接合部とも称す
る)ができる。このn型層8により、浅いPN接
合の一部に深いPN接合が形成される。深いPN
接合部8の形状はほとんど横の拡がりがないの
で、マスク6の窓5の形状によつて決まる。
Next, a 100 μm thick Mo mask 6 (FIG. 3) having a 150 μm×150 μm window 5 (FIG. 3) is placed on the surface of the semiconductor substrate 1. Thereafter, a laser beam 7 (FIG. 4) with increased energy of 2 J/cm 2 is projected onto the surface of the Si substrate. As is clear from FIG. 4, the entire substrate surface is covered with the Mo mask 6 except for the mask window 5, so that the high-energy laser beam is projected only onto the n-type Si layer exposed at the mask window. strength
When a high-energy laser beam of 2 J/cm 2 is projected for about 10 nsec, phosphorus in the area projected by the laser beam in the n-type Si layer 4 (Fig. 4) causes intra-solid diffusion, as shown in Fig. 4. 0.3μ deep into the board.
m) An n-type layer 8 (hereinafter also referred to as deep PN junction) is formed. This n-type layer 8 forms a deep PN junction in a part of the shallow PN junction. deep PN
The shape of the joint 8 is determined by the shape of the window 5 of the mask 6 since it has almost no lateral expansion.

この深いPN接合部8の表面に電極を形成する
にはSi基板表面にMoマスク6を固定した状態で、
金属蒸着装置(図示せず)内に設置し、まず、Si
基板を300℃に加熱しつつチタンを1000Åの厚さ
蒸着してチタン層9(第5図)を作り、更にその
上にAgを厚さ3μm蒸着してAg層10(第5図)
を形成する。蒸着が終了した後、Moマスク6を
Si基板表面から除くと、深いPN接合部8(第6
図)の表面にチタン−Ag二重層から成る電極1
1が形成できる。
To form an electrode on the surface of this deep PN junction 8, with the Mo mask 6 fixed on the Si substrate surface,
It is installed in a metal vapor deposition equipment (not shown), and first, Si
While heating the substrate to 300°C, titanium is evaporated to a thickness of 1000 Å to form a titanium layer 9 (Fig. 5), and on top of that, Ag is evaporated to a thickness of 3 μm to form an Ag layer 10 (Fig. 5).
form. After the vapor deposition is completed, apply Mo mask 6.
When removed from the Si substrate surface, deep PN junction 8 (sixth
Electrode 1 consisting of a titanium-Ag double layer on the surface of
1 can be formed.

この電極11は深いPN接合部8を形成する際
使用したマスク6をSi基板に対して移動させず
に、そのまま電極金属蒸着用マスクとして使用し
たために浅いPN接合部に重なることはなく、そ
の結果、電極形成の際に浅いPN接合が破壊する
ことはない。
This electrode 11 does not overlap the shallow PN junction because the mask 6 used when forming the deep PN junction 8 is not moved relative to the Si substrate and is used as a mask for electrode metal deposition. , the shallow PN junction will not be destroyed during electrode formation.

第7図乃至第8図は本発明の他の実施例を説明
する図である。本実施例の特長は1度のレーザ光
投射で浅いPN接合、深いPN接合部を形成する
点にある。
FIGS. 7 to 8 are diagrams for explaining other embodiments of the present invention. The feature of this embodiment is that a shallow PN junction and a deep PN junction can be formed by one laser beam projection.

第7図1はP型Si基板を示し、その表面にリン
のイオン打込みで形成した深さ0.1μmの不純物ド
ープ層2が存在している。不純物ドープ層2はイ
オンを打込んだ状態のままのため今まだ打込みイ
オンによる導電型を示していない。次にこのSi基
板表面にマスク12を載置する。本実施例で使用
したマスクは厚さ1mmのガラス板13の表面に所
定のパターンのAl蒸着膜(厚さ60Å)14を設
けた構成になつている。Al蒸着膜14の部分は
レーザ光に対し約50%の透過率を有する。これに
対し、Al蒸着膜15が設けられていないガラス
板部分のレーザ光に対する透過率はほぼ100%で
減衰がない。
FIG. 71 shows a P-type Si substrate, on the surface of which there is an impurity doped layer 2 with a depth of 0.1 μm formed by ion implantation of phosphorus. Since the impurity doped layer 2 remains in the state in which ions have been implanted, it has not yet shown the conductivity type due to the implanted ions. Next, a mask 12 is placed on the surface of this Si substrate. The mask used in this example has a structure in which a predetermined pattern of Al vapor deposited film (60 Å thick) 14 is provided on the surface of a glass plate 13 with a thickness of 1 mm. The portion of the Al deposited film 14 has a transmittance of about 50% to the laser beam. On the other hand, the transmittance of the laser beam in the portion of the glass plate where the Al vapor deposited film 15 is not provided is approximately 100% and there is no attenuation.

Al蒸着膜14側をSi基板表面側に対向させる
ようにマスク12をSi基板表面上に載置し、強度
2J/cm2のレーザ光7(第8図)を20n sec投射す
ると、マスク12のAl蒸着膜14(第8図)直
下の不純物ドープ層2は、約1J/cm2の透過レーザ
光によつて約20n sec投射され、ドープ層中のリ
ンが電気的に活性化して該領域のドープ層をN型
化する。一方、Al蒸着膜の存在しないガラス板
直下の不純物ドープ層2は、ほぼ2J/cm2の透過レ
ーザ光によつて約20n sec投射され、イオン打込
みされたリンが電気的に活性化して該ドープ層を
N型とすると共に、上記のリンが更にSi基板内に
深く拡散して深いPN接合部8を形成する。
The mask 12 is placed on the Si substrate surface so that the Al deposited film 14 side faces the Si substrate surface side, and the mask 12 is
When the laser beam 7 (FIG. 8) of 2 J/cm 2 is projected for 20 nsec, the impurity doped layer 2 directly under the Al deposited film 14 (FIG. 8) of the mask 12 is exposed to the transmitted laser beam of about 1 J/cm 2 . The doped layer is then irradiated for about 20 nsec, and phosphorus in the doped layer is electrically activated to make the doped layer in that region N-type. On the other hand, the impurity doped layer 2 directly under the glass plate, where no Al deposited film is present, is projected for about 20 nsec by a transmitted laser beam of about 2 J/cm 2 , and the ion-implanted phosphorus is electrically activated and the doped layer 2 is The layer is made N-type, and the phosphorus is further diffused deeply into the Si substrate to form a deep PN junction 8.

本実施例によれば半透膜マスクを使用すること
により二度必要だつたレーザ光投射工程を一度で
済ませることができ、生産性を更に高められる。
According to this embodiment, by using a semi-transparent film mask, the laser beam projection process that was previously required twice can be completed only once, and productivity can be further improved.

実施例に使用したマスクの透過率制御はAl等
の金属蒸着膜の厚さによつて制御することができ
る。
The transmittance of the mask used in the examples can be controlled by the thickness of the metal vapor deposited film such as Al.

本発明の他の実施例を第9図乃至第10図につ
いて説明する。半導体装置に於いて、電極層と半
導体基板との接続抵抗を下げることは半導体装置
の特性改善のために重要である。従来、この目的
のため電極用金属層を設ける前に、半導体基板表
面の電極形成部に高濃度に不純物を拡散して低抵
抗部にしておき、そこに電極用金属層を形成する
ことが行なわれている。この低抵抗層を形成する
方法は通常不純物の選択拡散法、イオン打込み法
等が利用されるが、製造工程が増え、しかも長時
間の処理となつて生産性の面から問題がある。
Another embodiment of the invention will be described with reference to FIGS. 9 and 10. In a semiconductor device, reducing the connection resistance between an electrode layer and a semiconductor substrate is important for improving the characteristics of the semiconductor device. Conventionally, for this purpose, before forming the electrode metal layer, impurities were diffused at a high concentration into the electrode forming area on the surface of the semiconductor substrate to make it a low resistance area, and then the electrode metal layer was formed there. It is. The method of forming this low-resistance layer usually uses a selective impurity diffusion method, an ion implantation method, etc., but this increases the number of manufacturing steps and requires a long processing time, which poses problems in terms of productivity.

本実施例は、電極抵抗を下げるに適した製法で
ある。
This example is a manufacturing method suitable for lowering electrode resistance.

第9図は、Si基板表面に浅いN型層4を設けた
基板1の表面に窓5を有するMoマスク6を載置
し、この状態でリンイオン15をマスクの窓5を
通して1×1016個/cm2の濃度でイオン打込みし、
高濃度不純物ドープ層16を形成した状態を示し
ている。次に第10図に示す様に、マスク6をそ
のままの状態に保ち、強度1.4J/cm2のレーザ光7
を22n sec投射する。このレーザ光投射により、
深いPN接合部17が形成される。この深いPN
接合部17の不純物濃度は高いために、その後の
処理で形成される電極層と半導体層との接続抵抗
は低くできる。
In FIG. 9, a Mo mask 6 having a window 5 is placed on the surface of a substrate 1 having a shallow N-type layer 4 on the surface of the Si substrate, and in this state, 1×10 16 phosphorus ions 15 are passed through the window 5 of the mask. Ion implantation was performed at a concentration of / cm2 ,
A state in which a layer 16 doped with high concentration impurities is formed is shown. Next, as shown in FIG. 10, the mask 6 is kept as it is and the laser beam 7 with an intensity of 1.4 J/cm
is projected for 22n sec. By this laser beam projection,
A deep PN junction 17 is formed. This deep PN
Since the impurity concentration in the junction portion 17 is high, the connection resistance between the electrode layer and the semiconductor layer formed in subsequent processing can be reduced.

第11図乃至第15図は本発明を太陽電池の製
作に応用した場合の実施例について示している。
比抵抗0.5〜10Ω・cmのP型Si基板1(第11図)
の表面に深さ0.1μmのN型層4(第11図)を形
成する。次に第12図に示した様に、任意形状の
窓18,19,20(断面図表示であるので、
個々独立した窓にみえるが、実際にはすべて連続
した窓である)を有するMoマスク21を載置す
る。このマスクに強度1.4J/cm2のレーザ光7(第
13図)を20n sec投射すると、窓の部分に露出
する層4中の不純物がSi基板内に深く拡散し、深
さ0.3μmのN型層8(第13図)を形成する。
FIGS. 11 to 15 show examples in which the present invention is applied to the production of solar cells.
P-type Si substrate 1 with a specific resistance of 0.5 to 10Ω・cm (Fig. 11)
An N-type layer 4 (FIG. 11) with a depth of 0.1 μm is formed on the surface. Next, as shown in FIG.
A Mo mask 21 having windows (which appear to be individual windows, but are actually all continuous windows) is placed. When a laser beam 7 (Fig. 13) with an intensity of 1.4 J/cm 2 is projected for 20 ns onto this mask, the impurities in the layer 4 exposed at the window are diffused deeply into the Si substrate, and the N A mold layer 8 (FIG. 13) is formed.

次に、マスク20を半導体基板から動かさずに
金属蒸着装置(図示せず)内で、Si基板を300℃
に加熱しつつ、まずチタンを1000Åの厚さ蒸着
し、続いてAgを3μmの厚さ蒸着する。層9(第1
4図)がチタン蒸着層で、層10(第14図)が
Ag蒸着層である。蒸着終了後Moマスク20(第
14図)を除去すると深いPN接合部8の表面に
チタン−Ag二重層から成る電極11(第15図)
が形成される。
Next, without moving the mask 20 from the semiconductor substrate, the Si substrate is heated to 300°C in a metal vapor deposition apparatus (not shown).
First, titanium was deposited to a thickness of 1000 Å, and then Ag was deposited to a thickness of 3 μm. Layer 9 (first
Figure 4) is the titanium vapor deposited layer, and layer 10 (Figure 14) is the titanium vapor deposited layer.
This is an Ag vapor deposited layer. When the Mo mask 20 (Fig. 14) is removed after the vapor deposition, an electrode 11 made of a titanium-Ag double layer is formed on the surface of the deep PN junction 8 (Fig. 15).
is formed.

以上の工程により、太陽電池の構造が得られ
る。
Through the above steps, a solar cell structure is obtained.

本実施例では次の効果を有する。(1)深いPN接
合部上に確実に電極が形成され、浅いPN接合部
上に電極が伸びることがないので製品歩留が高ま
る。(2)電極部以外のPN接合が半導体基板表面か
ら浅い位置にあるので、太陽光に対する光電変換
効率が高まる。特に、従来の太陽電池では極端に
低くかつた短波長光に対する光電変換効率を高め
ることができる。(3)加うるに電極層下のPN接合
が深いことは電極形成に伴なうリーク電流を抑え
(深いPN接合部の局部的破壊も起こらないた
め)、開放電圧を増大せしめることができる。(4)
深いPN接合形成のマスクを電極形成の蒸着マス
クとして兼用できるため生産性が向上する。
This embodiment has the following effects. (1) Electrodes are reliably formed on deep PN junctions and do not extend over shallow PN junctions, increasing product yield. (2) Since the PN junction other than the electrode part is located at a shallow position from the surface of the semiconductor substrate, the photoelectric conversion efficiency for sunlight is increased. In particular, the photoelectric conversion efficiency for short wavelength light, which is extremely low in conventional solar cells, can be increased. (3) In addition, the deep PN junction under the electrode layer suppresses the leakage current that accompanies electrode formation (because local breakdown of the deep PN junction does not occur) and increases the open circuit voltage. (Four)
Productivity is improved because the mask for forming deep PN junctions can also be used as a deposition mask for electrode formation.

本実施例で、第13図のレーザ光投射の前工程
として、マスク21を使用してN型不純物を高濃
度にイオン打込みする工程を加えると電極抵抗が
低くなり、それだけ損失を減ずることができる。
In this example, if a step of ion-implanting N-type impurities at a high concentration using a mask 21 is added as a pre-process to the laser beam projection shown in FIG. 13, the electrode resistance will be lowered, and the loss can be reduced accordingly. .

以上、本発明を本発明の代表的実施例について
説明したが、本発明は上記実施例に限られるもの
ではなく、本発明の技術思想の範囲内で種々変更
し得ること勿論である。例えば、本発明の実施例
では半導体基板としてSiについてのみ説明したが
別にSiに限られず、他の半導体基板、例えばGe、
GaAs、CdSe等の化合物半導体基板も実施可能で
ある。又電極金属もTi−Agの二重層のみならず
使用される半導体基板に適した電極金属が利用で
きる。
Although the present invention has been described above with reference to typical embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various changes can be made within the scope of the technical idea of the present invention. For example, in the embodiments of the present invention, only Si was described as the semiconductor substrate, but it is not limited to Si, and other semiconductor substrates such as Ge,
Compound semiconductor substrates such as GaAs and CdSe can also be used. Further, as for the electrode metal, not only the Ti-Ag double layer but also an electrode metal suitable for the semiconductor substrate used can be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第6図は本発明の実施例を説明する
要部拡大縦断面図、第7図乃至第8図は本発明の
他の実施例を説明する要部拡大縦断面図、第9図
乃至第10図は本発明の他の実施例を説明する要
部拡大縦断面図、第11図乃至第15図は本発明
の他の実施例を説明する要部拡大縦断面図であ
る。 1:P型Si基板、2:不純物ドープ層、3,
7:レーザ光、4:N型層、5,18,19,2
0:マスクの窓、6,21:金属マスク、8,1
7:深いPN接合部、9:チタン蒸着層、10:
Ag蒸着層、11:電極層、12:ガラスマスク、
13:ガラス板、14:Al蒸着膜、15:イオ
ンビーム、16:高濃度イオン打込み領域。
1 to 6 are enlarged vertical cross-sectional views of main parts for explaining an embodiment of the present invention, FIGS. 7 to 8 are enlarged longitudinal cross-sectional views of main parts for explaining other embodiments of the present invention, and FIG. 10 to 10 are enlarged longitudinal cross-sectional views of main parts for explaining other embodiments of the present invention, and FIGS. 11 to 15 are enlarged longitudinal cross-sectional views for main parts for explaining other embodiments of the present invention. 1: P-type Si substrate, 2: impurity doped layer, 3,
7: Laser light, 4: N-type layer, 5, 18, 19, 2
0: Mask window, 6, 21: Metal mask, 8, 1
7: Deep PN junction, 9: Titanium vapor deposition layer, 10:
Ag vapor deposition layer, 11: electrode layer, 12: glass mask,
13: glass plate, 14: Al deposited film, 15: ion beam, 16: high concentration ion implantation region.

Claims (1)

【特許請求の範囲】[Claims] 1 第1導電型を有する半導体基板の表面領域に
浅い第2導電型不純物層を形成する工程と、上記
半導体基板の表面に所望の形状の窓を有するマス
クを載置する工程と、上記マスクの窓を介して第
2導電型イオンを打込み、上記半導体基板の表面
領域内に多量の第2導電型イオンを含む領域を形
成する工程と、上記マスクの窓を介して上記半導
体基板にレーザー光を照射して上記多量の第2導
電型イオンを含む領域内の第2導電型イオンを上
記半導体基板内へ拡散させ深いPn接合を作る工
程と、上記窓を介して上記半導体基板の露出され
た表面に電極用金属を被着して電極金属層を形成
する工程からなることを特徴とする半導体装置の
製造方法。
1. A step of forming a shallow second conductivity type impurity layer in a surface region of a semiconductor substrate having a first conductivity type; a step of placing a mask having a window of a desired shape on the surface of the semiconductor substrate; a step of implanting ions of a second conductivity type through a window to form a region containing a large amount of ions of the second conductivity type in a surface region of the semiconductor substrate; and a step of applying a laser beam to the semiconductor substrate through the window of the mask. irradiating and diffusing second conductivity type ions in the region containing a large amount of second conductivity type ions into the semiconductor substrate to form a deep Pn junction; and exposing the exposed surface of the semiconductor substrate through the window. 1. A method for manufacturing a semiconductor device, comprising the step of depositing an electrode metal on the substrate to form an electrode metal layer.
JP8991779A 1979-07-17 1979-07-17 Manufacture of semiconductor device Granted JPS5615035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8991779A JPS5615035A (en) 1979-07-17 1979-07-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8991779A JPS5615035A (en) 1979-07-17 1979-07-17 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5615035A JPS5615035A (en) 1981-02-13
JPS633447B2 true JPS633447B2 (en) 1988-01-23

Family

ID=13984051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8991779A Granted JPS5615035A (en) 1979-07-17 1979-07-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5615035A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57136368A (en) * 1981-02-17 1982-08-23 Fujitsu Ltd Manufacture of mis transistor
JPS57138157A (en) * 1981-02-20 1982-08-26 Fujitsu Ltd Manufacture of semiconductor device
US4542580A (en) * 1983-02-14 1985-09-24 Prime Computer, Inc. Method of fabricating n-type silicon regions and associated contacts
KR100974221B1 (en) * 2008-04-17 2010-08-06 엘지전자 주식회사 Method for forming selective emitter of solar cell using laser annealing and Method for manufacturing solar cell using the same
KR101037316B1 (en) * 2010-09-30 2011-05-26 (유)에스엔티 Apparatus for forming selective emitter of solar cell
CN104170095B (en) * 2012-03-14 2016-10-19 Imec非营利协会 For the method manufacturing the photovoltaic cell with plating contact
JP2014072474A (en) * 2012-10-01 2014-04-21 Sharp Corp Method of manufacturing photoelectric conversion element and photoelectric conversion element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4926456A (en) * 1972-07-11 1974-03-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4926456A (en) * 1972-07-11 1974-03-08

Also Published As

Publication number Publication date
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