JPS6250972B2 - - Google Patents
Info
- Publication number
- JPS6250972B2 JPS6250972B2 JP54073379A JP7337979A JPS6250972B2 JP S6250972 B2 JPS6250972 B2 JP S6250972B2 JP 54073379 A JP54073379 A JP 54073379A JP 7337979 A JP7337979 A JP 7337979A JP S6250972 B2 JPS6250972 B2 JP S6250972B2
- Authority
- JP
- Japan
- Prior art keywords
- ion implantation
- ion
- impurities
- metal film
- implantation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 13
- 230000004913 activation Effects 0.000 description 5
- 230000003213 activating effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特に電
極部及びその直下に存在するイオン注入による不
純物の熱処理方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of heat treating impurities by ion implantation existing in an electrode portion and immediately below the electrode portion.
最近の半導体集積回路の高集積度化、高速度化
に伴ない、シリコン基板あるいは不純物導入層の
結晶性が素子特性に大きな影響を与えることはよ
く知られている。従来、MOSデバイスのソー
ス，ドレインの形成には拡散法あるいはイオン注
入法等が用いられてきた。特に素子の微細化に伴
つて、浅い接合が必要とされる場合にはイオン注
入法が有効である。 It is well known that with the recent increase in the degree of integration and speed of semiconductor integrated circuits, the crystallinity of a silicon substrate or an impurity-introduced layer has a great influence on device characteristics. Conventionally, diffusion methods, ion implantation methods, etc. have been used to form sources and drains of MOS devices. Ion implantation is particularly effective when shallow junctions are required as devices become smaller.
ところが、イオン注入法により高濃度に不純物
を導入した場合には、その後のプロセスとして、
注入された不純物を活性化するための熱処理工程
が必要となる。というのは、所定濃度以上の不純
物のイオン注入によつて形成されたイオン注入層
は、不純物が添加された非晶質シリコン層となる
が、この状態では不純物原子は単にシリコン中に
注入されただけでシリコン原子と置き換わつては
おらず、電気伝導に寄与しないからである。そこ
で、イオン注入層の熱処理を行なつて、不純物を
シリコン原子と置き換え、不純物が電気伝導に寄
与し得る状態にする（不純物を活性化する）。 However, when impurities are introduced at a high concentration by ion implantation, as a subsequent process,
A heat treatment step is required to activate the implanted impurities. This is because an ion-implanted layer formed by ion-implanting impurities at a predetermined concentration or higher becomes an amorphous silicon layer with impurities added, but in this state the impurity atoms are simply implanted into the silicon. This is because they do not replace silicon atoms and do not contribute to electrical conduction. Therefore, the ion-implanted layer is heat-treated to replace the impurities with silicon atoms, thereby making the impurities capable of contributing to electrical conduction (activating the impurities).
従来、注入された不純物を活性化するための熱
処理工程としては、半導体装置全体を熱処理炉内
で熱処理する方法が用いられている。しかし、こ
のような従来行なわれてきた熱処理炉を用いる通
常の熱処理方法の場合には、イオン注入法の特徴
である不純物の浅い急峻な分布が、熱拡散するこ
とにより損なわれ、かつ残留損傷も多く100％近
い活性化率を得ることは困難である。 Conventionally, as a heat treatment process for activating implanted impurities, a method has been used in which the entire semiconductor device is heat treated in a heat treatment furnace. However, in the case of conventional heat treatment methods using heat treatment furnaces, the shallow and steep distribution of impurities, which is a characteristic of ion implantation, is lost due to thermal diffusion, and residual damage may also occur. It is difficult to obtain an activation rate close to 100% in many cases.
本発明の目的は上記したような諸欠点を解消さ
せること、つまりイオン注入層の不純物の該イオ
ン注入層への拡散を防ぎ、導入された不純物の活
性化率を向上せしめ、かつ電極部金属と前記イオ
ン注入層とのオーミツク性の問題をも同時に解決
せしめる方法を提供することにある。 The purpose of the present invention is to eliminate the above-mentioned drawbacks, that is, to prevent impurities in the ion-implanted layer from diffusing into the ion-implanted layer, to improve the activation rate of the introduced impurities, and to improve the activation rate of the impurities introduced into the ion-implanted layer. The object of the present invention is to provide a method that simultaneously solves the ohmic problem with the ion-implanted layer.
本発明の特徴は、半導体基板の一表面上の所望
部分にイオン注入法で形成された不純物を含む領
域（即ち、イオン注入層）及びその直上に金属材
料で形成された電極、配線等を具備した半導体装
置において、前記半導体基板の一表面とは逆の表
面から、半導体基板を透過し前記イオン注入層に
吸収される光（例えばCO2レーザ等）を、前記イ
オン注入層と前記金属膜との界面に向けて照射す
ることにより、前記イオン注入層にエネルギーを
加え、前記イオン注入層と金属膜の前記イオン注
入層側の部分とを熱処理することにある。 The present invention is characterized by comprising a region containing impurities (i.e., an ion implantation layer) formed by ion implantation in a desired portion on one surface of a semiconductor substrate, and electrodes, wiring, etc. formed of a metal material directly above the region. In the semiconductor device, light (for example, CO 2 laser, etc.) that passes through the semiconductor substrate and is absorbed by the ion implantation layer is applied to the ion implantation layer and the metal film from a surface opposite to the one surface of the semiconductor substrate. The method is to apply energy to the ion-implanted layer by irradiating the ion-implanted layer toward the interface thereof, thereby heat-treating the ion-implanted layer and a portion of the metal film on the ion-implanted layer side.
本発明はイオン注入層が一般に非晶質となつて
おり、その光エネルギーの吸収係数が半導体基板
のそれよりも大であり、そのことによりイオン注
入層だけが選択的に前記光のエネルギーの吸収を
受けることを利用し、該イオン注入層の不純物の
活性化を行なう。 In the present invention, the ion implantation layer is generally amorphous, and its light energy absorption coefficient is larger than that of the semiconductor substrate, so that only the ion implantation layer selectively absorbs the light energy. The impurities in the ion-implanted layer are activated by utilizing the effect of the ion implantation.
以下、本発明について図面を参照して説明す
る。 Hereinafter, the present invention will be explained with reference to the drawings.
第１図に本発明の原理図を示す。試料の構造は
図示した如く、シリコン基板３の一表面上に、例
えばイオン注入法等を用いて不純物２が添加され
ており、その上に金属膜１が付着されている。上
記試料の裏面から、シリコン基板をほとんど透過
するような光（例えば波長10.6μｍのCO2レーザ
光、あるいはその他の赤外線源。シリコンの吸収
波長の上端が約1.1μｍであるので照射光の波長
は約1.2μｍ以上であればよい。）を光源４より照
射することにより、金属―シリコン界面５の近傍
で上記光エネルギーを吸収せしめ、上記不純物含
有量の添加原子を活性化すると共に、上記金属膜
の熱処理を行なう。 FIG. 1 shows a diagram of the principle of the present invention. As shown in the figure, the structure of the sample is such that an impurity 2 is added onto one surface of a silicon substrate 3 using, for example, an ion implantation method, and a metal film 1 is attached thereon. Light that almost passes through the silicon substrate from the back side of the sample (for example, CO 2 laser light with a wavelength of 10.6 μm, or other infrared light source. Since the upper end of the absorption wavelength of silicon is about 1.1 μm, the wavelength of the irradiated light is 1.2 μm or more) from the light source 4, the light energy is absorbed in the vicinity of the metal-silicon interface 5, activating the added atoms of the impurity content, and the metal film Heat treatment is performed.
本発明は従来行なわれている電気炉を用いた熱
処理方法に比較して、下記するような幾つかの長
所を有している。 The present invention has several advantages over the conventional heat treatment method using an electric furnace, as described below.
ごく短時間（msecオーダー）の熱処理であ
る。従来の方法では、900℃〜1000℃の電気炉
による熱処理が少なくとも30分は必要であつ
た。 This is a very short heat treatment (on the order of milliseconds). Conventional methods require heat treatment in an electric furnace at 900°C to 1000°C for at least 30 minutes.
不純物が添加されている領域だけ選択的に光
エネルギーの吸収を受ける。 Light energy is selectively absorbed only in the region to which impurities are added.
添加不純物の活性化率がほぼ100％である。
従来の方法では、90〜95％の活性化率である。 The activation rate of added impurities is almost 100%.
Conventional methods have an activation rate of 90-95%.
金属膜は、シリコンとの界面に近い部分がよ
り熱処理されるため、熱処理中の雰囲気の影響
を受けにくい。それ故、酸化性雰囲気に弱い金
属膜でも十分に耐え得る。 Since the metal film is heat-treated more closely at the interface with silicon, it is less affected by the atmosphere during heat treatment. Therefore, even a metal film that is weak against an oxidizing atmosphere can withstand it satisfactorily.
金属とシリコンのコンタクト部におけるオー
ミツク性が非常にすぐれている。 Excellent ohmic properties at the contact area between metal and silicon.
次に、本発明の実施例としてMOSデバイスに
適用された例を第２図に示す。この実施例におい
ても、裏面から照射された光により、フイールド
酸化膜６に隣接するソース，ドレイン領域の添加
不純物を100％活性化させ、電極部金属１の熱処
理も同時に行なつて、金属膜の抵抗値を大幅に下
げると共に、オーミツクなコンタクトを得ること
ができた。 Next, FIG. 2 shows an example in which the present invention is applied to a MOS device. In this embodiment as well, the added impurities in the source and drain regions adjacent to the field oxide film 6 are activated by 100% by light irradiated from the back surface, and the electrode metal 1 is also heat-treated at the same time, so that the metal film is In addition to significantly lowering the resistance value, we were able to obtain an ohmic contact.
第３図に金属／シリコンのコンタクト抵抗率を
従来の電気炉を用いて熱処理を行なつた場合と、
本発明による熱処理との比較を示す。熱処理後の
コンタクト抵抗率は、本発明の方法が従来法に比
べ約２桁程度低いことが判る。 Figure 3 shows the metal/silicon contact resistivity when heat treated using a conventional electric furnace, and
A comparison with heat treatment according to the present invention is shown. It can be seen that the contact resistivity after heat treatment is about two orders of magnitude lower in the method of the present invention than in the conventional method.
さて、今まで説明してきた金属膜としては何ら
特別な限定を設ける必要はなかつたが、モリブデ
ン，タングステンあるいはその他の高融点金属を
金属膜として用いた場合には本発明の特徴が更に
発揮される。これは上述した光熱処理によつて、
基板シリコンの一部が溶融した場合でも、シリコ
ン上に付着している金属膜は昇華あるいは蒸発す
ることがないからである。 Now, there is no need to set any special limitations on the metal film that has been explained so far, but the features of the present invention can be further demonstrated when molybdenum, tungsten, or other high-melting point metals are used as the metal film. . This is achieved by the photothermal treatment mentioned above.
This is because even if part of the silicon substrate melts, the metal film attached to the silicon will not sublimate or evaporate.
以上MOSデバイスを例にした場合の結果であ
つたが、本発明は上記デバイスに限定されること
なく、イオン注入法により不純物を導入して形成
されたイオン注入層を有するバイポーラあるいは
その他のデバイスへ適用できることは言うまでも
ない。又、上述した説明では基板材料としてシリ
コンを用いてきたが、本発明が他の材料―例えば
ゲルマニウム、化合物半導体（ガリウム・アーセ
ナイド等）―を用いた場合でも有効であることは
言うまでもない。 Although the above results are based on an example of a MOS device, the present invention is not limited to the above device, but can be applied to bipolar or other devices having an ion-implanted layer formed by introducing impurities by ion implantation. Needless to say, it can be applied. Furthermore, although silicon has been used as the substrate material in the above description, it goes without saying that the present invention is also effective when other materials such as germanium and compound semiconductors (gallium arsenide, etc.) are used.
以上説明したように、本発明によれば、ごく短
時間の光照射で、イオン注入層の不純物の活性化
を、該イオン注入層外への不純物の拡散を生ぜし
めることなく、完全に行なうことができる。金属
膜は、前記イオン注入層に近い部分のみが、該イ
オン注入層の光吸収による熱による処理を受ける
ため、酸化性雰囲気に弱い金属膜でも十分に使用
に耐え得ると共に、該金属膜と前記イオン注入層
とのコンタクト部におけるオーミツク性も非常に
すぐれたものとなる。 As explained above, according to the present invention, impurities in an ion-implanted layer can be completely activated by light irradiation for a very short time without causing diffusion of impurities outside the ion-implanted layer. Can be done. Since only the portion of the metal film close to the ion-implanted layer is subjected to heat treatment due to light absorption by the ion-implanted layer, even a metal film that is weak in an oxidizing atmosphere can withstand use sufficiently, and the metal film and the The ohmic properties at the contact portion with the ion-implanted layer are also very excellent.
第１図は本発明の原理を示すもので、不純物が
添加されたシリコン基板上に金属膜が付着されて
おり、裏面から光を照射させた場合の断面図を示
す。第２図は本発明をMOSデバイスへ適用させ
た実施例の断面図を示す。第３図は本発明の効果
を説明するための金属／シリコンのコンタクト抵
抗率（Ω・cm2）を示した図である。
尚、図において、１……金属膜、２……不純物
添加層（イオン注入層）、３……シリコン基板、
４……光源、５……金属―シリコン界面、６……
酸化膜を各々示す。
FIG. 1 shows the principle of the present invention, and shows a cross-sectional view of a silicon substrate doped with impurities, in which a metal film is attached, and light is irradiated from the back side. FIG. 2 shows a sectional view of an embodiment in which the present invention is applied to a MOS device. FIG. 3 is a diagram showing metal/silicon contact resistivity (Ω·cm 2 ) for explaining the effects of the present invention. In the figure, 1... metal film, 2... impurity doped layer (ion implantation layer), 3... silicon substrate,
4...Light source, 5...Metal-silicon interface, 6...
Each oxide film is shown.
Claims (1)
入法を用いて不純物を導入して形成したイオン注
入層と、前記所定の領域を含む前記一表面の部分
上に形成された金属膜とを有する半導体装置にお
いて、前記半導体基板の前記一表面とは逆の表面
から、前記半導体基板を透過し前記イオン注入層
に吸収される光を、前記イオン注入層と前記金属
膜との界面に向けて照射し、前記イオン注入層と
前記金属膜の前記イオン注入層側の部分とを熱処
理することを特徴とする半導体装置の製造方法。 ２ 前記光はレーザビームあるいは赤外光である
ことを特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。 ３ 金属膜は、モリブデン，タングステン等の高
融点金属（1400℃以上の融点を有する金属）であ
ることを特徴とする特許請求の範囲第１項、もし
くは第２項記載の半導体装置の製造方法。[Scope of Claims] 1. An ion implantation layer formed by introducing impurities into a predetermined region of one surface of a semiconductor substrate using an ion implantation method, and an ion implantation layer formed on a portion of the one surface including the predetermined region. In the semiconductor device, light transmitted through the semiconductor substrate and absorbed by the ion implantation layer from a surface opposite to the one surface of the semiconductor substrate is transmitted to the ion implantation layer and the metal film. 1. A method of manufacturing a semiconductor device, characterized in that the ion implantation layer and a portion of the metal film on the ion implantation layer side are heat-treated by irradiating the ion implantation layer toward an interface thereof. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the light is a laser beam or infrared light. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the metal film is a high melting point metal (metal having a melting point of 1400° C. or higher) such as molybdenum or tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7337979A JPS55165640A (en) | 1979-06-11 | 1979-06-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7337979A JPS55165640A (en) | 1979-06-11 | 1979-06-11 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55165640A JPS55165640A (en) | 1980-12-24 |
| JPS6250972B2 true JPS6250972B2 (en) | 1987-10-28 |
Family
ID=13516485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7337979A Granted JPS55165640A (en) | 1979-06-11 | 1979-06-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55165640A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH028485U (en) * | 1988-06-29 | 1990-01-19 | ||
| JPH0250363U (en) * | 1988-10-03 | 1990-04-09 | ||
| JPH0250362U (en) * | 1988-10-03 | 1990-04-09 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH027422A (en) * | 1988-06-24 | 1990-01-11 | Ricoh Co Ltd | High-temperature heat treatment by laser |
| JP2005183604A (en) * | 2003-12-18 | 2005-07-07 | Semiconductor Leading Edge Technologies Inc | Method for heat treatment of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4825816A (en) * | 1971-08-11 | 1973-04-04 |
-
1979
- 1979-06-11 JP JP7337979A patent/JPS55165640A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4825816A (en) * | 1971-08-11 | 1973-04-04 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH028485U (en) * | 1988-06-29 | 1990-01-19 | ||
| JPH0250363U (en) * | 1988-10-03 | 1990-04-09 | ||
| JPH0250362U (en) * | 1988-10-03 | 1990-04-09 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55165640A (en) | 1980-12-24 |
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