JPH113969A - チップ部品が積層された基板部品 - Google Patents

チップ部品が積層された基板部品

Info

Publication number
JPH113969A
JPH113969A JP9156497A JP15649797A JPH113969A JP H113969 A JPH113969 A JP H113969A JP 9156497 A JP9156497 A JP 9156497A JP 15649797 A JP15649797 A JP 15649797A JP H113969 A JPH113969 A JP H113969A
Authority
JP
Japan
Prior art keywords
chip
component
substrate
board
chip component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9156497A
Other languages
English (en)
Japanese (ja)
Other versions
JPH113969A5 (enExample
Inventor
Tsutomu Mitani
力 三谷
Tsukasa Shiraishi
司 白石
Yoshihiro Bessho
芳宏 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9156497A priority Critical patent/JPH113969A/ja
Publication of JPH113969A publication Critical patent/JPH113969A/ja
Publication of JPH113969A5 publication Critical patent/JPH113969A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP9156497A 1997-06-13 1997-06-13 チップ部品が積層された基板部品 Pending JPH113969A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9156497A JPH113969A (ja) 1997-06-13 1997-06-13 チップ部品が積層された基板部品

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9156497A JPH113969A (ja) 1997-06-13 1997-06-13 チップ部品が積層された基板部品

Publications (2)

Publication Number Publication Date
JPH113969A true JPH113969A (ja) 1999-01-06
JPH113969A5 JPH113969A5 (enExample) 2005-03-03

Family

ID=15629056

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9156497A Pending JPH113969A (ja) 1997-06-13 1997-06-13 チップ部品が積層された基板部品

Country Status (1)

Country Link
JP (1) JPH113969A (enExample)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4705206A (en) * 1984-05-21 1987-11-10 Nippondenso Co., Ltd. Method for brazing a magnesium-containing aluminum alloy
JP2001035994A (ja) * 1999-07-15 2001-02-09 Toshiba Corp 半導体集積回路装置およびシステム基板
WO2004049439A1 (ja) * 2002-11-26 2004-06-10 Renesas Technology Corp. 半導体装置
KR100442699B1 (ko) * 2002-07-19 2004-08-02 삼성전자주식회사 인접 수동소자 칩이 전기적으로 연결된 웨이퍼, 수동소자및 이를 이용한 반도체 패키지
EP1187210A3 (en) * 2000-09-07 2005-03-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device
JP2006093419A (ja) * 2004-09-24 2006-04-06 Oki Electric Ind Co Ltd 半導体装置及びその実装方法
JP2006156909A (ja) * 2004-12-01 2006-06-15 Renesas Technology Corp マルチチップモジュール
JP2006261603A (ja) * 2005-03-18 2006-09-28 Ricoh Co Ltd マルチチップ型半導体装置及びその製造方法
JP2008028004A (ja) * 2006-07-19 2008-02-07 Toshiba Corp 半導体装置
JP2009092545A (ja) * 2007-10-10 2009-04-30 Panasonic Corp 角速度および加速度検出用複合センサ
JP2009521803A (ja) * 2005-12-23 2009-06-04 テッセラ，インコーポレイテッド 超ファインピッチ配線で積層された超小型電子アセンブリ
US7598618B2 (en) 2006-03-15 2009-10-06 Oki Semiconductor Co., Ltd. Semiconductor device
JP2009260373A (ja) * 2009-07-27 2009-11-05 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法及び半導体基板
US7911064B2 (en) 2005-03-07 2011-03-22 Panasonic Corporation Mounted body and method for manufacturing the same
US8039305B2 (en) 2007-04-27 2011-10-18 Sumitomo Bakelite Company, Ltd. Method for bonding semiconductor wafers and method for manufacturing semiconductor device
JP2012502476A (ja) * 2008-09-08 2012-01-26 インテル・コーポレーション メインボードに直接取着されたダイをパッケージが被覆しているメインボード構造
WO2019076993A1 (en) 2017-10-17 2019-04-25 Next Generation Rail Technologies S.L. SYSTEM FOR DETECTING EVENTS OR SITUATIONS HAVING ASSOCIATED MODELS OF ACOUSTIC VIBRATIONS IN A RAIL RAIL AND VIBRATION DETECTION UNIT FOR SAID SYSTEM

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4705206A (en) * 1984-05-21 1987-11-10 Nippondenso Co., Ltd. Method for brazing a magnesium-containing aluminum alloy
JP2001035994A (ja) * 1999-07-15 2001-02-09 Toshiba Corp 半導体集積回路装置およびシステム基板
EP1187210A3 (en) * 2000-09-07 2005-03-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US7211469B2 (en) 2002-07-19 2007-05-01 Samsung Electronics Co., Ltd. Semiconductor wafer having electrically connected passive device chips, passive devices and semiconductor package using the same
KR100442699B1 (ko) * 2002-07-19 2004-08-02 삼성전자주식회사 인접 수동소자 칩이 전기적으로 연결된 웨이퍼, 수동소자및 이를 이용한 반도체 패키지
US6943430B2 (en) 2002-07-19 2005-09-13 Samsung Electronics Co., Ltd Semiconductor wafer having electrically connected passive device chips, passive devices and semiconductor package using the same
WO2004049439A1 (ja) * 2002-11-26 2004-06-10 Renesas Technology Corp. 半導体装置
JP2006093419A (ja) * 2004-09-24 2006-04-06 Oki Electric Ind Co Ltd 半導体装置及びその実装方法
JP2006156909A (ja) * 2004-12-01 2006-06-15 Renesas Technology Corp マルチチップモジュール
US7911064B2 (en) 2005-03-07 2011-03-22 Panasonic Corporation Mounted body and method for manufacturing the same
JP2006261603A (ja) * 2005-03-18 2006-09-28 Ricoh Co Ltd マルチチップ型半導体装置及びその製造方法
JP2009521803A (ja) * 2005-12-23 2009-06-04 テッセラ，インコーポレイテッド 超ファインピッチ配線で積層された超小型電子アセンブリ
US7598618B2 (en) 2006-03-15 2009-10-06 Oki Semiconductor Co., Ltd. Semiconductor device
JP2008028004A (ja) * 2006-07-19 2008-02-07 Toshiba Corp 半導体装置
US8039305B2 (en) 2007-04-27 2011-10-18 Sumitomo Bakelite Company, Ltd. Method for bonding semiconductor wafers and method for manufacturing semiconductor device
JP2009092545A (ja) * 2007-10-10 2009-04-30 Panasonic Corp 角速度および加速度検出用複合センサ
US9069000B2 (en) 2007-10-10 2015-06-30 Panasonic Intellectual Property Management Co., Ltd. Composite sensor for detecting angular velocity and acceleration
US9453851B2 (en) 2007-10-10 2016-09-27 Panasonic Intellectual Property Management Co., Ltd. Composite sensor for detecting angular velocity and acceleration
JP2012502476A (ja) * 2008-09-08 2012-01-26 インテル・コーポレーション メインボードに直接取着されたダイをパッケージが被覆しているメインボード構造
DE112009002155B4 (de) 2008-09-08 2023-10-19 Sk Hynix Nand Product Solutions Corp. Computersystem mit einer Hauptplatinenbaugruppe mit einem Gehäuse über einem direkt auf der Hauptplatine angebrachten Chip und Verfahren zu dessen Herstellung
JP2009260373A (ja) * 2009-07-27 2009-11-05 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法及び半導体基板
WO2019076993A1 (en) 2017-10-17 2019-04-25 Next Generation Rail Technologies S.L. SYSTEM FOR DETECTING EVENTS OR SITUATIONS HAVING ASSOCIATED MODELS OF ACOUSTIC VIBRATIONS IN A RAIL RAIL AND VIBRATION DETECTION UNIT FOR SAID SYSTEM

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