JPH09180445A - プログラム可能時間遅延装置 - Google Patents

プログラム可能時間遅延装置

Info

Publication number
JPH09180445A
JPH09180445A JP8320402A JP32040296A JPH09180445A JP H09180445 A JPH09180445 A JP H09180445A JP 8320402 A JP8320402 A JP 8320402A JP 32040296 A JP32040296 A JP 32040296A JP H09180445 A JPH09180445 A JP H09180445A
Authority
JP
Japan
Prior art keywords
delay
time delay
signal
time
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8320402A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09180445A5 (enExample
Inventor
Danny R Cline
アール．クライン ダニー
Kuong Hua Hii
ファ ヒィ クオング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH09180445A publication Critical patent/JPH09180445A/ja
Publication of JPH09180445A5 publication Critical patent/JPH09180445A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
  • Networks Using Active Elements (AREA)
  • Logic Circuits (AREA)
JP8320402A 1995-11-29 1996-11-29 プログラム可能時間遅延装置 Withdrawn JPH09180445A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US767695P 1995-11-29 1995-11-29
US007676 1995-11-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007101792A Division JP4279888B2 (ja) 1995-11-29 2007-04-09 プログラム可能時間遅延装置

Publications (2)

Publication Number Publication Date
JPH09180445A true JPH09180445A (ja) 1997-07-11
JPH09180445A5 JPH09180445A5 (enExample) 2004-11-18

Family

ID=21727534

Family Applications (2)

Application Number Title Priority Date Filing Date
JP8320402A Withdrawn JPH09180445A (ja) 1995-11-29 1996-11-29 プログラム可能時間遅延装置
JP2007101792A Expired - Lifetime JP4279888B2 (ja) 1995-11-29 2007-04-09 プログラム可能時間遅延装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2007101792A Expired - Lifetime JP4279888B2 (ja) 1995-11-29 2007-04-09 プログラム可能時間遅延装置

Country Status (5)

Country Link
US (2) US5841707A (enExample)
EP (1) EP0777232B1 (enExample)
JP (2) JPH09180445A (enExample)
KR (1) KR970029840A (enExample)
DE (1) DE69626752T2 (enExample)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
JP4198201B2 (ja) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ 半導体装置
US5917760A (en) * 1996-09-20 1999-06-29 Sldram, Inc. De-skewing data signals in a memory system
US6088774A (en) 1996-09-20 2000-07-11 Advanced Memory International, Inc. Read/write timing for maximum utilization of bidirectional read/write bus
US5953263A (en) * 1997-02-10 1999-09-14 Rambus Inc. Synchronous memory device having a programmable register and method of controlling same
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
KR100261215B1 (ko) * 1997-07-29 2000-07-01 윤종용 클럭 버퍼 및 이를 포함하는 메모리 로직 복합 반도체장치
US6101197A (en) 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
JPH11154398A (ja) * 1997-11-20 1999-06-08 Oki Electric Ind Co Ltd 半導体記憶装置
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US5923613A (en) * 1998-03-18 1999-07-13 Etron Technology, Inc. Latched type clock synchronizer with additional 180°-phase shift clock
US6052746A (en) * 1998-04-14 2000-04-18 Motorola, Inc. Integrated circuit having programmable pull device configured to enable/disable first function in favor of second function according to predetermined scheme before/after reset
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6111812A (en) 1999-07-23 2000-08-29 Micron Technology, Inc. Method and apparatus for adjusting control signal timing in a memory device
KR100355229B1 (ko) * 2000-01-28 2002-10-11 삼성전자 주식회사 카스 명령의 동작 지연 기능을 구비한 반도체 메모리 장치및 이에 적용되는 버퍼와 신호전송 회로
JP3647364B2 (ja) 2000-07-21 2005-05-11 Ｎｅｃエレクトロニクス株式会社 クロック制御方法及び回路
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7068564B2 (en) * 2003-06-29 2006-06-27 International Business Machines Corporation Timer lockout circuit for synchronous applications
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7283005B2 (en) * 2004-02-10 2007-10-16 Stmicroelectronics S.R.L. Clock-pulse generator circuit
JP4960807B2 (ja) * 2007-08-28 2012-06-27 セイコーインスツル株式会社 可変周波数発振回路
KR101144864B1 (ko) * 2010-10-12 2012-05-14 알에프코어 주식회사 실시간 지연 장치
CN114374377A (zh) * 2022-01-11 2022-04-19 长鑫存储技术有限公司 延时电路

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059814A (ja) * 1983-09-12 1985-04-06 Hitachi Ltd プログラマブル遅延回路およびこれを用いた半導体集積回路装置
JPS61237512A (ja) * 1985-04-12 1986-10-22 Nec Ic Microcomput Syst Ltd 半導体集積回路
US4894626A (en) * 1988-09-30 1990-01-16 Advanced Micro Devices, Inc. Variable length shift register
US5068553A (en) * 1988-10-31 1991-11-26 Texas Instruments Incorporated Delay stage with reduced Vdd dependence
US5028824A (en) * 1989-05-05 1991-07-02 Harris Corporation Programmable delay circuit
JPH03219719A (ja) * 1990-01-24 1991-09-27 Mitsubishi Electric Corp 遅延回路及びそれを用いた半導体装置
US5051630A (en) * 1990-03-12 1991-09-24 Tektronix, Inc. Accurate delay generator having a compensation feature for power supply voltage and semiconductor process variations
US5202642A (en) * 1991-05-09 1993-04-13 Iomega Corporation Apparatus and method for fractional frequency division
US5465076A (en) * 1991-10-04 1995-11-07 Nippondenso Co., Ltd. Programmable delay line programmable delay circuit and digital controlled oscillator
JP2982928B2 (ja) * 1992-04-01 1999-11-29 三菱電機株式会社 半導体記憶装置
JPH0612877A (ja) * 1992-06-18 1994-01-21 Toshiba Corp 半導体集積回路
US5281927A (en) * 1993-05-20 1994-01-25 Codex Corp. Circuit and method of controlling a VCO with capacitive loads
US5459422A (en) * 1993-06-02 1995-10-17 Advanced Micro Devices, Inc. Edge selective delay circuit
FR2718903B1 (fr) * 1994-04-13 1996-05-24 Bull Sa Circuit à retard réglable.
KR0138208B1 (ko) * 1994-12-08 1998-04-28 문정환 반도체 메모리 소자
JPH0969292A (ja) * 1995-08-30 1997-03-11 Nec Corp 半導体記憶装置
JPH1064275A (ja) * 1996-08-27 1998-03-06 Nkk Corp 遅延回路、ａｔｄパルス発生回路、及びそれを用いた半導体記憶装置

Also Published As

Publication number Publication date
US6002286A (en) 1999-12-14
EP0777232A2 (en) 1997-06-04
JP4279888B2 (ja) 2009-06-17
EP0777232B1 (en) 2003-03-19
KR970029840A (ko) 1997-06-26
EP0777232A3 (en) 1999-08-04
DE69626752T2 (de) 2003-11-20
US5841707A (en) 1998-11-24
DE69626752D1 (de) 2003-04-24
JP2007228617A (ja) 2007-09-06

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