JPH058570B2 - - Google Patents

Info

Publication number
JPH058570B2
JPH058570B2 JP57226135A JP22613582A JPH058570B2 JP H058570 B2 JPH058570 B2 JP H058570B2 JP 57226135 A JP57226135 A JP 57226135A JP 22613582 A JP22613582 A JP 22613582A JP H058570 B2 JPH058570 B2 JP H058570B2
Authority
JP
Japan
Prior art keywords
layer
metal layer
metal
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57226135A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59117135A (ja
Inventor
Masayuki Sato
Kensuke Nakada
Minoru Enomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57226135A priority Critical patent/JPS59117135A/ja
Publication of JPS59117135A publication Critical patent/JPS59117135A/ja
Publication of JPH058570B2 publication Critical patent/JPH058570B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05557Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05563Only on parts of the surface of the internal layer
    • H01L2224/05564Only on the bonding interface of the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
JP57226135A 1982-12-24 1982-12-24 半導体装置の製造方法 Granted JPS59117135A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57226135A JPS59117135A (ja) 1982-12-24 1982-12-24 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57226135A JPS59117135A (ja) 1982-12-24 1982-12-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59117135A JPS59117135A (ja) 1984-07-06
JPH058570B2 true JPH058570B2 (fr) 1993-02-02

Family

ID=16840393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57226135A Granted JPS59117135A (ja) 1982-12-24 1982-12-24 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59117135A (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61141155A (ja) * 1984-12-14 1986-06-28 Hitachi Ltd はんだ下地電極
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
JP2533634B2 (ja) * 1989-01-31 1996-09-11 松下電器産業株式会社 バンプ電極を備える半導体装置の製造方法
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5268072A (en) * 1992-08-31 1993-12-07 International Business Machines Corporation Etching processes for avoiding edge stress in semiconductor chip solder bumps
JPH07105586B2 (ja) * 1992-09-15 1995-11-13 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チップ結合構造
US5376584A (en) * 1992-12-31 1994-12-27 International Business Machines Corporation Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
US5384283A (en) * 1993-12-10 1995-01-24 International Business Machines Corporation Resist protection of ball limiting metal during etch process
JP2664878B2 (ja) * 1994-01-31 1997-10-22 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チップパッケージおよびその製造方法
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
EP0815593B1 (fr) * 1995-03-20 2001-12-12 Unitive International Limited Procedes de fabrication de perles de soudure et structures comprenant une couche barriere en titane
JP2011249564A (ja) * 2010-05-27 2011-12-08 Renesas Electronics Corp 半導体装置の製造方法及び実装構造

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572548A (en) * 1980-06-06 1982-01-07 Citizen Watch Co Ltd Ic electrode structure
JPS57198647A (en) * 1981-06-01 1982-12-06 Nec Corp Semiconductor device and manufacture therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572548A (en) * 1980-06-06 1982-01-07 Citizen Watch Co Ltd Ic electrode structure
JPS57198647A (en) * 1981-06-01 1982-12-06 Nec Corp Semiconductor device and manufacture therefor

Also Published As

Publication number Publication date
JPS59117135A (ja) 1984-07-06

Similar Documents

Publication Publication Date Title
US5492235A (en) Process for single mask C4 solder bump fabrication
US3997963A (en) Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads
JP6406975B2 (ja) 半導体素子および半導体装置
JPH058570B2 (fr)
JP2653179B2 (ja) 集積回路装置用バンプ電極の製造方法
JPS59198734A (ja) 多層配線構造
JPH04229618A (ja) 集積回路デバイスの接点及びその形成方法
JPS6112047A (ja) 半導体装置の製造方法
JPH0730095A (ja) 半導体装置及びその製造方法
JPH03101234A (ja) 半導体装置の製造方法
JPH0697663B2 (ja) 半導体素子の製造方法
JPH05283412A (ja) 半導体装置,およびその製造方法
JP2564827B2 (ja) 半導体装置及びその製造方法
JPS5810836A (ja) 半導体装置
JP3074760B2 (ja) 金属バンプの形成方法
JPS60214538A (ja) 半導体チツプの搭載方法
JPH0590271A (ja) バンプ電極形成方法
KR100212496B1 (ko) 플립칩용 반도체 장치의 제조방법
JPH0715909B2 (ja) 半導体装置の製造方法
JP2003100800A (ja) シリコンチップの電極構造
JPS61239647A (ja) 半導体装置
JPH0695543B2 (ja) 半導体装置及びその製造方法
JPH05144814A (ja) 半導体集積回路装置の製造方法
JPS6297348A (ja) 半導体装置の製造方法
JPH0815153B2 (ja) 半導体素子の突起電極形成方法