JPH0555479B2 - - Google Patents

Info

Publication number
JPH0555479B2
JPH0555479B2 JP61012944A JP1294486A JPH0555479B2 JP H0555479 B2 JPH0555479 B2 JP H0555479B2 JP 61012944 A JP61012944 A JP 61012944A JP 1294486 A JP1294486 A JP 1294486A JP H0555479 B2 JPH0555479 B2 JP H0555479B2
Authority
JP
Japan
Prior art keywords
silicon
thickness
substrate
deposition
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61012944A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61174196A (ja
Inventor
Furanshisu Kooboi Junia Jon
Reon Jasutoruzebusuki Rubomiru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of JPS61174196A publication Critical patent/JPS61174196A/ja
Publication of JPH0555479B2 publication Critical patent/JPH0555479B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/025—Deposition multi-step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP61012944A 1985-01-23 1986-01-22 単結晶シリコンの被着法 Granted JPS61174196A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/694,100 US4592792A (en) 1985-01-23 1985-01-23 Method for forming uniformly thick selective epitaxial silicon
US694100 2003-10-27

Publications (2)

Publication Number Publication Date
JPS61174196A JPS61174196A (ja) 1986-08-05
JPH0555479B2 true JPH0555479B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-08-17

Family

ID=24787400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61012944A Granted JPS61174196A (ja) 1985-01-23 1986-01-22 単結晶シリコンの被着法

Country Status (2)

Country Link
US (1) US4592792A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS61174196A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166071A (ja) * 1985-01-17 1986-07-26 Toshiba Corp 半導体装置及びその製造方法
US4698316A (en) * 1985-01-23 1987-10-06 Rca Corporation Method of depositing uniformly thick selective epitaxial silicon
US4735918A (en) * 1985-05-24 1988-04-05 Hughes Aircraft Company Vertical channel field effect transistor
US4857479A (en) * 1985-10-08 1989-08-15 Motorola Method of making poly-sidewall contact transistors
JP2662396B2 (ja) * 1986-03-31 1997-10-08 キヤノン株式会社 結晶性堆積膜の形成方法
CA1329756C (en) * 1986-04-11 1994-05-24 Yutaka Hirai Method for forming crystalline deposited film
EP0251767A3 (en) * 1986-06-30 1988-09-07 Canon Kabushiki Kaisha Insulated gate type semiconductor device and method of producing the same
KR900007686B1 (ko) * 1986-10-08 1990-10-18 후지쓰 가부시끼가이샤 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘층과 다결정 실리콘층을 동시에 성장시키는 기상 증착방법
JP2651146B2 (ja) * 1987-03-02 1997-09-10 キヤノン株式会社 結晶の製造方法
EP0289246A1 (en) * 1987-04-27 1988-11-02 Seiko Instruments Inc. Method of manufacturing MOS devices
US4786615A (en) * 1987-08-31 1988-11-22 Motorola Inc. Method for improved surface planarity in selective epitaxial silicon
US5255258A (en) * 1987-09-24 1993-10-19 Canon Kabushiki Kaisha Microprobe, preparation thereof and electronic device by use of said microprobe
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features
US4873205A (en) * 1987-12-21 1989-10-10 International Business Machines Corporation Method for providing silicide bridge contact between silicon regions separated by a thin dielectric
US4859626A (en) * 1988-06-03 1989-08-22 Texas Instruments Incorporated Method of forming thin epitaxial layers using multistep growth for autodoping control
US4882294A (en) * 1988-08-17 1989-11-21 Delco Electronics Corporation Process for forming an epitaxial layer having portions of different thicknesses
US4963506A (en) * 1989-04-24 1990-10-16 Motorola Inc. Selective deposition of amorphous and polycrystalline silicon
DE3918060A1 (de) * 1989-06-02 1990-12-06 Licentia Gmbh Verfahren zur herstellung kapazitaetsarmer bipolarbauelemente
US5234861A (en) * 1989-06-30 1993-08-10 Honeywell Inc. Method for forming variable width isolation structures
US5017999A (en) * 1989-06-30 1991-05-21 Honeywell Inc. Method for forming variable width isolation structures
US4923826A (en) * 1989-08-02 1990-05-08 Harris Corporation Method for forming dielectrically isolated transistor
JPH0671073B2 (ja) * 1989-08-29 1994-09-07 株式会社東芝 半導体装置及びその製造方法
EP0430514B1 (en) * 1989-11-27 1996-01-31 AT&T Corp. Substantially facet free selective epitaxial growth process
US5168089A (en) * 1989-11-27 1992-12-01 At&T Bell Laboratories Substantially facet-free selective epitaxial growth process
US6139483A (en) * 1993-07-27 2000-10-31 Texas Instruments Incorporated Method of forming lateral resonant tunneling devices
JP3272532B2 (ja) * 1993-12-27 2002-04-08 富士通株式会社 半導体装置の製造方法
US5427630A (en) * 1994-05-09 1995-06-27 International Business Machines Corporation Mask material for low temperature selective growth of silicon or silicon alloys
US6225666B1 (en) 1999-10-29 2001-05-01 National Semiconductor Corporation Low stress active area silicon island structure with a non-rectangular cross-section profile and method for its formation
JP2001250944A (ja) 2000-03-07 2001-09-14 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7855126B2 (en) * 2004-06-17 2010-12-21 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a cyclic selective epitaxial growth technique and semiconductor devices formed using the same
US7361563B2 (en) * 2004-06-17 2008-04-22 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a selective epitaxial growth technique
KR100593736B1 (ko) * 2004-06-17 2006-06-28 삼성전자주식회사 단결정 반도체 상에 선택적으로 에피택시얼 반도체층을형성하는 방법들 및 이를 사용하여 제조된 반도체 소자들
US20070048956A1 (en) * 2005-08-30 2007-03-01 Tokyo Electron Limited Interrupted deposition process for selective deposition of Si-containing films
CN101165225B (zh) * 2007-08-28 2010-06-02 河北普兴电子科技股份有限公司 一种ic片外延的工艺方法
KR101714003B1 (ko) 2010-03-19 2017-03-09 삼성전자 주식회사 패시티드 반도체패턴을 갖는 반도체소자 형성방법 및 관련된 소자
CN102386067B (zh) * 2010-08-31 2013-12-18 中国科学院上海微系统与信息技术研究所 有效抑制自掺杂效应的外延生长方法
JP6579710B2 (ja) * 2015-12-24 2019-09-25 昭和電工株式会社 ＳｉＣエピタキシャルウェハの製造方法
CN106757324B (zh) * 2016-12-26 2019-05-21 南京国盛电子有限公司 一种硅外延片的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL271203A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1960-01-15
US3850707A (en) * 1964-09-09 1974-11-26 Honeywell Inc Semiconductors
US3511702A (en) * 1965-08-20 1970-05-12 Motorola Inc Epitaxial growth process from an atmosphere composed of a hydrogen halide,semiconductor halide and hydrogen
US3425879A (en) * 1965-10-24 1969-02-04 Texas Instruments Inc Method of making shaped epitaxial deposits
US3764409A (en) * 1969-09-29 1973-10-09 Hitachi Ltd Method for fabricating a semiconductor component for a semiconductor circuit
US3661636A (en) * 1970-04-22 1972-05-09 Ibm Process for forming uniform and smooth surfaces
US3945864A (en) * 1974-05-28 1976-03-23 Rca Corporation Method of growing thick expitaxial layers of silicon
US4412868A (en) * 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
US4400411A (en) * 1982-07-19 1983-08-23 The United States Of America As Represented By The Secretary Of The Air Force Technique of silicon epitaxial refill
US4522662A (en) * 1983-08-12 1985-06-11 Hewlett-Packard Company CVD lateral epitaxial growth of silicon over insulators

Also Published As

Publication number Publication date
JPS61174196A (ja) 1986-08-05
US4592792A (en) 1986-06-03

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Legal Events

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LAPS Cancellation because of no payment of annual fees