GB2113465A - Method for growing monocrystalline silicon on a masking layer - Google Patents

Method for growing monocrystalline silicon on a masking layer Download PDF

Info

Publication number
GB2113465A
GB2113465A GB08236936A GB8236936A GB2113465A GB 2113465 A GB2113465 A GB 2113465A GB 08236936 A GB08236936 A GB 08236936A GB 8236936 A GB8236936 A GB 8236936A GB 2113465 A GB2113465 A GB 2113465A
Authority
GB
United Kingdom
Prior art keywords
silicon
accordance
masking layer
etching
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08236936A
Other versions
GB2113465B (en
Inventor
John Francis Corboy
Lubomir Leon Jastrzebski
Scott Carlton Blackstone
Robert Henry Pagliaro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23326867&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=GB2113465(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by RCA Corp filed Critical RCA Corp
Publication of GB2113465A publication Critical patent/GB2113465A/en
Application granted granted Critical
Publication of GB2113465B publication Critical patent/GB2113465B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02642—Mask materials other than SiO2 or SiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

An apertured masking layer (14) is disposed on the surface (12) of a substrate (10), and an epitaxial layer (20) is then grown by a depositing/etching cycle. By performing the depositing/ etching cycle a predetermined number of times, monocrystalline silicon (20) will he grown from the surface (18) of the substrate (10), through the aperture (16) in the mask (14), and over the masking layer (14). The etching removes any polycrystalline deposits. <IMAGE>

Description

SPECIFICATION Method for growing monocrystalline silicon on a masking layer The present invention relates to a method for epitaxially forming a layer of monocrystalline silicon. More particularly, it relates to a process for fabricating monocrystalline silicon on an apertured masking layer which is disposed on a monocrystalline substrate.
In the field of processing semiconductive devices, epitaxially deposited silicon is commonly used in a variety of applications. Basically, this deposition involves the precipitation of silicon from a gaseous source onto a crystalline lattice, such that the deposited silicon forms a structure which continues the crystalline lattice. Conventionally used gaseous sources of silicon include silane (SiH4), silicon tetrachloride (SiCI4), trichlorosilane (SiHCl3), and dichlorosilane (SiH2CI2), and the details of typical processing are described in ADVANCES IN DICHLOROSILANE EPITAXIAL TECHNOLOGY, D.J. DeLong, Solid State Technology, October 1972, pp.29-34,41, and in U.S. Patent No.3,945,864, METHOD OF GROWING THICK EPITAXIAL LAYERS OF SILICON, N. Goldsmith et al., issued March 1976.The quality and rate of the depositing silicon is a strong function of such parameters as depositional temperature and specific composition of the gas, as elaborated upon in U.S. Patent No. 3,239,372, METHOD OF PRODUCING SINGLE CRYSTALLINE SILICON, E. Sirtl, issued March 8, 1966, as well as in the previously cited references.
Epitaxial films of silicon have been selectively grown within the apertures of a silicon dioxide (SiO2) mask on the surface of a substrate of a single-crystalline silicon. An example of such a process is described in SELECTIVE EPITAXIAL DEPOSITION OF SILICON, B.D. Joyce et al., Nature, Vol. 195, pp.485-6, August 4, 1962. Selective epitaxial deposition has also been used to form a grid of monocrystalline-silicon islands wherein the grid is specified by a particular center-to-center spacing of an array of apertures in a silicon dioxide layer, and wherein each silicon island overgrows the silicon dioxide surrounding each aperture a specific distance. An example of such an overgrown structure and its manufacturing method is described in THE "EPICON" ARRAY: A NEW SEMICONDUCTOR ARRAY-TYPE CAMERA TUBE STRUCTURE, W.E.Engeler at al., Applied Physics Letters, Vol. 16, No.5, March 1,1970; THE EPICON CAMERATUBE: AN EPITAXIAL DIODE ARRAY VIDICON, S.M. Blumenfeld eta., IEEE Trans., Vol. ED18, No. 11, November1971; and in U.S.
Patent No. 3,746,908, SOLID STATE LIGHT SENSITIVE STORAGE ARRAY, W. E. Engeler, issued July 17, 1973.
As suggested by the cited references, the process of epitaxially depositing monocrystalline silicon is well established in the semiconductor industry. For example, the effect of the temperation of reaction, deposition-gas composition, and gaseous flow rate on both the quality and deposition rate is well characterized. It is well known that while monocrystalline silicon will nucleate on a monocrystalline substrate, a monocrystalline layer will not nucleate on a polycrystalline or amorphous surface. Typically, when a non-single-crystalline surface, such as the surface of a silicon dioxide layer, is subjected to an epitaxial-depositing environment, a non-single-crystalline silicon film will be deposited.
Heretofore, the formation of monocrystalline silicon on silicon dioxide was achieved by creating a grid of monocrystalline-silicon islands as disclosed by Engeler and Blumenfeld. This process relies on the migration of silicon torts across the oxide surface bwetween the silicon islands so as to add to the growth of the islands. If at a particular temperature the migration distance of the precipitating silicon is less than half the distance between silicon islands, nucleation of non-single-crystalline silicon will occur on the oxide between the monocrystalline-silicon islands. In an effort to avoid the formation of a non-single-crystalline silicon layer, and provide a deposition process which is not constrained by the geometry of the epitaxial nucleation site or sites or the growth time, the present invention was discovered.
A masking layer is provided on a semiconductive substrate, wherein the masking layer includes at least one aperture which exposes a monocrystalline portion of the substrate. Silicon is then epitaxially deposited from a gaseous mixture which comprises a silicon-source gas, and a carrier gas. The substrate is next exposed to a gaseous mixture comprising an etching gas and a carrier gas such that a portion of the previously deposited silicon is etched. This depositing and etching cycle is then repeated an appropriate number of times so as to achieve a monocrystalline silicon layer of predetermined size on the masking layer.
In the drawing: Figures 1 and 2 illustrate the processing sequence of the present invention.
Figures 3, 4, 5 and 6 illustrate alternative structures which can be fabricated by the present invention.
As illustrated in Figure 1, a substrate 10 having a substantially planar surface 12 is initially provided. In the preferred embodiment, the material of the substrate 10 is monocrystalline silicon, and the surface 12 represents a major crystallographic surface. However, the material of the substrate 10 is not limited to silicon, as will be discussed subsequently. An apertured mask 14, which in the preferred embodiment comprises a silicon dioxide (SiO2) layer of approximately 0.1 to 1.0 micron in thickness, is disposed on the substrate surface 12. Silicon dioxide is selected as a masking material because it is amorphous and it can physically withstand subsequent epitaxial-deposition processing. Additionally, an SiO2 mask 14 can be readily formed, and apertures can be readily generated therein by conventional photolithographic processing.However, it should be recognized that the present invention is not limited to the use of SiO2, nor is it limited to a mask of a particular thickness. The important physical characteristics of the mask 14 are that it be non-single-crystalline and that it be capable of withstanding the temperatures encountered during subsequent processing. Other suitable masking materials include, for example, silicon nitride and aluminum oxide.
In Figure 1, the mask 14 includes a plurality of apertures 16. The size, spacing, and configuration of these apertures 16 can vary. Furthermore, although the embodiment illustrated in Figure 1 shows a plurality of apertures 16, the present invention requires only that a single aperture 16 be present. This multi-apertured embodiment is shown only by way of example. The illustrated apertures 16 might comprise, for example, a plurality of squares, circles or stripes.
The portion of the substrate surface 12 exposed by each aperture 16 will hereinafter be referred to as a nucleation site 18. The nucleation sites 18 in Figure 1 can be located anywhere along the surface 12. The only restriction is that each nucleation site 18 be monocrystalline in structure. This can be achieved, for example, by providing a substrate 10 of bulk monocrystalline material; a monocrystalline layer across the surface 12 of an otherwise non-single-crystalling substrate 10; or a polycrystalline surface 12 wherein the grain size is such that each aperture 16 can be defined within the boundaries of a grain.
The masked structure of Figure 1 is then subjected to a two stage, silicon depositing/etching cycle. In the first stage, hereinafter the depositing stage, silicon is deposited from a gaseous mixture which includes a silicon-source gas and a carrier gas. Additionally, a silicon-etching gas can be included during the depositing stage. In the second stage, hereinafter the etching stage, a portion of the silicon deposited during the first stage is etched in a gaseous mixture of a silicon-etching gas and a carrier gas. This depositing/etching cycle is then repeated, if desired, any number of times, until a monocrystalline-silicon layer of predetermined size is formed on the masking layer 14.At each nucleation site 18, crystalline growth will proceed substantially vertically (perpendicular to the surface 12) through the thickness of the mask 14, and then additionally will proceed laterally, across the surface of the mask 14. Repetition of the cycle will eventually yield a monocrystalline-silicon island 20 at each nucleation site 18, as illustrated in Figure 2.
The depositing/etching cycle can be performed within a conventional reactor, at atmospheric or reduced pressure, and a variety of silicon-source gases, silicon-etching gases, and carrier gases can be used. Using dichlorosilane as the silicon-source gas, HCI as the etching gas (in both stages), and hydrogen as the carrier gas, exemplary depositing/etching parameters are summarized in the table below.
FLOW RATE (liters/min) H2 HCI SiH2Cl2 TIME (min) DEPOSITING CYCLE 24 0.15 0.20 2 ETCHING CYCLE 24 0.30 1 FLOW VELOCITY: 24 cm/sec REACTOR TEMPERATURE: 1 1000C (pyrometer reading) PRESSURE: 1 atm These parameters were observed to produce a vertical growth rate of approximately 1.0 micron/min and a horizontal-to-vertical growth rate ratio of 1.5.
The vertical growth rate, horizontal-to-vertical growth-rate ratio, and the determination of whether to use a silicon-etching gas during the depositing cycle vary as a function of silicon-source gas and flow rate, silicon-etching gas and flow rate, depositing-cycle time, etching-cycle time, flow velocity, reactor temperature, and depositing pressure. For example, using SiH2Cl2 as the silicon-source gas, the vertical growth rate can be varied between approximately 0.4 and 2.0 microns/min by varying the SiH2Cl2 flow rate between approximately 0.10 and 1.0 liter/min and appropriately adjusting the silicon-etching gas flow rate during the depositing stage.
The horizontal-to-vertical growth-rate ratio generally increases at lower reacting temperatures. For example, using the parameters indicated in the table, the horizontal-to-vertical growth-rate ratio was observed to vary between approximately 1.0 and 2.2 as the temperature in the reactor was varied from 12000Cto 10500C.
The extent to which the temperature in the reactor influences growth rate and the horizontal-to-vertical growth-rate ratio also depends on the silicon-source gas used and the depositing pressure. For example, it is expected that SiH4 would permit depositions at lower temperature than would SiH2Cl2, while SiCI4 would permit depositions at higher temperatures than SiH2CI2. Depositing pressure might be varied, for example, from approximately 100 Torr to atmospheric pressure.
The indicated depositing and etching times can also be varied as a function of composition of the gas and temperature. For example, it is expected that a practical range of depositing times would be approximately from 30 seconds to 4 minutes, and that a practical range for etching-cycle times is approximately 20 seconds to 2 minutes.
During the depositing stage of the described depositing/etching process, silicon precipitates from the silicon-source gas onto all exposed surfaces of the substrate and mask. The silicon that deposits on each nucleation site 18 follows the monocrystalline lattice structure at that site. In contrast, the silicon which precipitates onto the mask 14 has no preferred orientation and therefore deposits in the form of isolated non-single-crystalline aggregates. Additionally, we have observed that at the indicated parameters, deposition of the monocrystalline silicon begins immediately while there is a delay of some critical time before the non-single-crystalline deposition occurs on the mask 14.
The presence of a silicon-etching gas such as HCI during the depositing cycle decreases the probability of non-single-crystalline silicon deposits forming on the mask 14 during deposition. During the depositing stage, the relative quantity of silicon-source gas and silicon-etching gas, and the depositing time, must be balanced, so as to achieve a practical monocrystalline-silicon growth rate while retaining the ability to subsequently remove, during the etching stage, the non-single-crystalline silicon which deposits on the mask 14.
The gaseous composition and duration of the etching stage of the depositing/etching process is designed so as to completely remove all of the non-single-crystalline aggregates which remain on the mask 14 following the depositing stage. Although this etching also removes some of the monocrystalline silicon growing from the nucleating sites 18, the rate of dissolution of this monocrystalline silicon is relatively low compared to the rate of dissolution of the non-single-crystalline aggregates. Thus, after a single depositing/etching cycle, more silicon is deposited during the depositing stage than is etched during the etching stage, and all of the deposited material is monocrystalline in nature.
The vertical/horizontal monocrystalline growth provided by the described depositing/etching process, permits the fabrication of a variety of useful semiconductor structures. The structure of Figure 2 might be used, for example, to form a plurality of individual, selectively-located semiconductor devices. Such devices might be fabricated, for example, by selectively doping the substrate 10 and silicon island 20 by conventional semiconductor processing techniques. For example, the interface between each silicon island 20 and the substrate 10 can be made rectifying or non-rectifying depending upon doping, and internal doping profiles within each silicon island 20 and within the substrate 10 can be manipulated using conventional photolithographic techniques.
Figures 3 through 6 illustrate alternative structures which can be fabricated by the process of the present invention. By continuing the described depositing/etching process on the structure of Figure 2, the plurality of silicon islands 20 will eventually grow together so as to form a continuous monocrystalline silicon layer 22, as illustrated in Figure 3. Figure 5 illustrates that a similar structure, of a monocrystalline silicon layer 22 overlying mask 14, can be fabricated from a single nucleation site 18 exposed by a single aperture 16 in the mask 14.
Figure 4 represents an alternative embodiment which potentially can be of great significance in the design of integrated circuits. It can be formed by etching cavities 24 in the silicon layer 22 of Figure 3 in areas corresponding to the apertures 16. In the illustrated embodiment, the cavities 24 extend through the thickness of the silicon layer 22 and through the epitaxial silicon within each aperture 16 so as to expose the substrate surface 12. Thus, if the geometry of the apertures 16 is so designed, a plurality of electrically isolated silicon islands 26 can be generated. A structure of this type might be effectively utilized in a silicon-on-sapphire type (SOS-type) application wherein a plurality of monocrystalline silicon islands are generated on an insulating substrate.Additionally, depending upon the application to which the structure of Figure 4 will be put, the cavities 24 subsequently can be filled with a dielectric, resistive, or conducting material, so as to yield a more planar structure.
It should be recognized that the structure of Figure 4 could similarly be fabricated from the single-aperture structure of Figure 5. Also, cavities similarly could be formed in the structure of Figure 2 or in a structure intermediate between those illustrated in Figure 2 and Figure 3.
Figure 6 illustrates an example of a multilevel structure which might be fabricated by the present invention. Isolated monocrystalline-silicon islands 26 are fabricated on the apertured mask 14 by the described depositing/etching process. An aperture mask 28 is subsequently formed on the silicon islands 26, and a second set of silicon islands 30 are then epitaxially overgrown thereon in a similar manner. A cavity or plurality of cavities 24 can be formed so as to isolate the silicon islands 26 and/or the silicon islands 30, as desired. Thus, the depositing/etching process of the present invention permits the fabrication of multilevel integrated circuits, each level being selectively isolated by, for example, an SiO2 mask. This can provide a strong impact on the potential packing density and level of integration of future integrated circuits.
It should be recognized that the embodiments disclosed herein are shown for exemplary purposes and are not intended to limit the scope of the present invention. A large variety of single or multilevel structures can be made using the depositing/etching process disclosed herein.

Claims (18)

1. A method for forming monocrystalline silicon over a masking layer comprising the steps of: providing a semiconductor substrate having a monocrystalline portion at the surface thereof and having a masking layer on said surface, the masking layer having an aperture over said monocrystalline portion; depositing silicon from a gaseous mixture comprising a silicon-source gas and a carrier gas; etching a portion of the deposited silicon in a gaseous mixture comprising a silicon-etching gas and a carrier gas; and repeating said depositing and etching cycle, so as to achieve a monocrystalline-silicon island extending from the surface of said substrate at the aperture of said masking layer and overlapping the masking layer a predetermined distance.
2. A method in accordance with Claim 1, further comprising: including a silicon-etching gas in the gaseous mixture which comprises the silicon-source gas and carrier gas.
3. A method in accordance with Claim 1, wherein the substrate is monocrystalline material.
4. A method in accordance with Claim 1,wherein the substrate is polycrystalline material having a grain size greater than the size of the aperture of said masking layer and further comprising: locating the mask aperture within the boundaries of a grain.
5. A method in accordance with Claim 1, further comprising: the masking layer including a plurality of apertures, each aperture being located over a monocrystalline portion of the substrate.
6. A method in accordance with Claim 1,wherein: the masking layer comprises a material selected from the group consisting of SiO2, Si3N4, and Awl203.
7. A method in accordance with Claim 1,wherein: the silicon-source gas is selected from the group consisting of SiCI4, SiH2Cl2, SiHCl3, and SiH4.
8. Amethod in accordance with Claim 1,wherein: the depositing gaseous mixture comprises approximately 0.6 volume percent silicon-source gas,0.6 volume percent HCI, and 98.8 volume percent H2.
9. A method in accordance with Claim 1, wherein: the etching gaseous mixture comprises approximately 1.2 volume percent HCI and 98.8 volume percent H2.
10. A method in accordance with Claim 1, comprising: depositing and etching within a reactor wherein the temperature range is between approximately 1050 C and 1200 C.
11. A method in accordance with Claim 1, wherein the depositing and etching cycle comprises: depositing for approximately 30 seconds to 4 minutes; and etching for approximately 20 seconds to 2 minutes.
12. A method in accordance with Claim 1, wherein the silicon-etching gas comprises HCI.
13. A method in accordance with Claim 1, wherein the carrier gas comprises hydrogen.
14. A method in accordance with Claims 1 or 5, comprising: repeating the depositing and etching cycle so as to form a layer of monocrystalline silicon over substantially the entire masking layer.
15. A method in accordance with Claims 1 or 5, further comprising: removing the silicon overlying each aperture of said masking layer so as to expose the surface of said substrate and form a cavity between portions of deposited monocrystalline silicon.
16. A method in accordance with Claim 15 further comprising: filling each of said cavities with a preselected material.
17. A method in accordance with Claim 15, further comprising: forming a second apertured masking layer, the second masking layer being located on the surface of the deposited monocrystalline silicon portions; and repeating the depositing and etching cycle of Claim 1 so as to achieve at each aperture in the second masking layer a monocrystalline silicon island extending from the surface of the deposited monocrystallinesilicon portion and overlapping the second masking layer a predetermined distance.
18. The method for forming monocrystalline silicon over a masking layer substantially as described hereinbefore and shown in Figures 1 through 6 of the accompanying drawing.
GB08236936A 1982-01-12 1982-12-30 Method for growing monocrystalline silicon on a masking layer Expired GB2113465B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33895882A 1982-01-12 1982-01-12

Publications (2)

Publication Number Publication Date
GB2113465A true GB2113465A (en) 1983-08-03
GB2113465B GB2113465B (en) 1986-08-06

Family

ID=23326867

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08236936A Expired GB2113465B (en) 1982-01-12 1982-12-30 Method for growing monocrystalline silicon on a masking layer

Country Status (8)

Country Link
JP (1) JPS58120595A (en)
DE (1) DE3300716A1 (en)
FR (1) FR2522695B1 (en)
GB (1) GB2113465B (en)
IN (1) IN157312B (en)
IT (1) IT1173651B (en)
SE (1) SE462756B (en)
YU (1) YU6083A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0252757A2 (en) * 1986-07-11 1988-01-13 Canon Kabushiki Kaisha Photoelectric conversion device
US4829016A (en) * 1987-10-19 1989-05-09 Purdue Research Foundation Bipolar transistor by selective and lateral epitaxial overgrowth
US5403771A (en) * 1990-12-26 1995-04-04 Canon Kabushiki Kaisha Process for producing a solar cell by means of epitaxial growth process
CN115198352A (en) * 2022-08-24 2022-10-18 西安奕斯伟材料科技有限公司 Epitaxial growth method and epitaxial wafer

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214424A (en) * 1985-07-11 1987-01-23 Fujitsu Ltd Manufacture of semiconductor device
JP3272532B2 (en) * 1993-12-27 2002-04-08 富士通株式会社 Method for manufacturing semiconductor device
JP4832022B2 (en) * 2005-07-29 2011-12-07 株式会社日立国際電気 Substrate processing equipment
JP2010141079A (en) * 2008-12-11 2010-06-24 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor device
JP2010147142A (en) * 2008-12-17 2010-07-01 Hitachi Kokusai Electric Inc Method for manufacturing semiconductor, and apparatus
JP2012054364A (en) * 2010-08-31 2012-03-15 Nobuyuki Akiyama Manufacturing method of silicon thin film, manufacturing method of silicon thin film solar cell, silicon thin film, silicon thin film solar cell

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL260072A (en) * 1960-01-15
US3746608A (en) * 1963-05-14 1973-07-17 Nitto Boseki Co Ltd Shaped article of synthetic resin having mechanically disordered orientation
DE2059116C3 (en) * 1970-12-01 1974-11-21 Siemens Ag, 1000 Berlin Und 8000 Muenchen Method for manufacturing a semiconductor component
US3945864A (en) * 1974-05-28 1976-03-23 Rca Corporation Method of growing thick expitaxial layers of silicon
DE3008058A1 (en) * 1980-03-03 1981-09-17 Robert Bosch Gmbh, 7000 Stuttgart Monolithic integrated circuit mfr. - by partial etching and refilling of conductor zones through mask

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0252757A2 (en) * 1986-07-11 1988-01-13 Canon Kabushiki Kaisha Photoelectric conversion device
EP0252757A3 (en) * 1986-07-11 1988-08-31 Canon Kabushiki Kaisha Photoelectric conversion device
AU609405B2 (en) * 1986-07-11 1991-05-02 Canon Kabushiki Kaisha Photoelectric conversion device
US5610094A (en) * 1986-07-11 1997-03-11 Canon Kabushiki Kaisha Photoelectric conversion device
US4829016A (en) * 1987-10-19 1989-05-09 Purdue Research Foundation Bipolar transistor by selective and lateral epitaxial overgrowth
US5403771A (en) * 1990-12-26 1995-04-04 Canon Kabushiki Kaisha Process for producing a solar cell by means of epitaxial growth process
CN115198352A (en) * 2022-08-24 2022-10-18 西安奕斯伟材料科技有限公司 Epitaxial growth method and epitaxial wafer
CN115198352B (en) * 2022-08-24 2024-03-26 西安奕斯伟材料科技股份有限公司 Epitaxial growth method and epitaxial wafer

Also Published As

Publication number Publication date
GB2113465B (en) 1986-08-06
JPH0435439B2 (en) 1992-06-11
SE8300040L (en) 1983-07-13
JPS58120595A (en) 1983-07-18
FR2522695A1 (en) 1983-09-09
DE3300716A1 (en) 1983-07-21
SE8300040D0 (en) 1983-01-04
IN157312B (en) 1986-03-01
DE3300716C2 (en) 1993-01-21
FR2522695B1 (en) 1987-02-27
YU6083A (en) 1985-10-31
IT8319043A0 (en) 1983-01-10
IT1173651B (en) 1987-06-24
SE462756B (en) 1990-08-27

Similar Documents

Publication Publication Date Title
US4549926A (en) Method for growing monocrystalline silicon on a mask layer
US4578142A (en) Method for growing monocrystalline silicon through mask layer
US3620833A (en) Integrated circuit fabrication
US4698316A (en) Method of depositing uniformly thick selective epitaxial silicon
US4592792A (en) Method for forming uniformly thick selective epitaxial silicon
KR100231764B1 (en) Method for forming contact portion of semiconductor device
US3884733A (en) Dielectric isolation process
US5130778A (en) Semiconductor article and preparation thereof
GB2113465A (en) Method for growing monocrystalline silicon on a masking layer
JP2685028B2 (en) Method for manufacturing semiconductor device
EP0190581B1 (en) Vertically isolated complementary transistor structures
EP0252757A2 (en) Photoelectric conversion device
AU651568B2 (en) Method for forming crystalline deposited film
JPH02191320A (en) Crystal product and its manufacture
EP0405896A2 (en) Process for growing crystal
US5525536A (en) Method for producing SOI substrate and semiconductor device using the same
EP0193298A2 (en) Method for the formation of epitaxial layers for integrated circuits
US3702790A (en) Monolithic integrated circuit device and method of manufacturing the same
Pribat et al. Conformal vapor phase epitaxy
Chang Autodoping in silicon epitaxy
JP3206943B2 (en) Method of manufacturing SOI substrate and semiconductor device
JPS63239932A (en) Crystal forming method
CN112820636B (en) Semiconductor structure, self-supporting gallium nitride layer and preparation method thereof
JPH0113210B2 (en)
JPH0583173B2 (en)

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19971230