JPH0435439B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical field to which the invention relates] The present invention relates to a method of epitaxially forming a layer of single crystal silicon, and more specifically, to a method of epitaxially forming a layer of single crystal silicon on a mask layer with holes formed on a single crystal substrate. The present invention relates to a method of producing silicon. BACKGROUND OF THE INVENTION In the field of semiconductor device manufacturing, epitaxially deposited silicon is widely used in a variety of applications. Basically, this deposition involves depositing silicon from a gas source onto a crystal lattice such that the deposited silicon forms a structure continuous with the crystal lattice of the substrate. Commonly used silicon gas sources include silane (S _i H ₄ ), silicon tetrachloride (S _i Cl ₄ ), and trichlorosilane (S _i
HCl ₃ ) and dichlorosilane (S _i H ₂ Cl ₂ ), and their typical treatments are described in ``ADVANCES
IN DICHLOROSILANE EPITAXIAL
TECHNO-LOGY” by DJ Delong Solid State Technology
State Tech-nology) Monthly issue 197210 pp.29-34,
41 and US Pat. No. 3,945,864 to Goldsmith et al.
Silicon quality and deposition rate are a function of deposition temperature and gas composition, as detailed in E. Sirtl, U.S. Pat. . (Prior Art) Silicon epitaxial films are made from silicon dioxide (S _{i )} on the surface of a single crystal silicon substrate.
O ₂ ) was grown selectively during the apertures of the mask. An example of such a method is “SELECTIVE Epitaxial Deposition of Silicon”.
EPITAXIAL DEPOSITION OF SILICON)
BDJoyce et al. (Nature, Vol. 195, pp. 485-6, August 4, 1962 issue)
detailed in. Selective epitaxial deposition techniques have also been used to form a lattice of monocrystalline silicon islands defined by specific center spacings of an array of openings in a silicon dioxide layer. Each silicon island is grown over a certain distance over the silicon dioxide surrounding each opening. Such a superimposed growth structure and its manufacturing method are known as the “Epicon Array New Semiconductor Array Image Tube Structure (THE
“EPICON” ARRAY:A NEW
SEMICONDUCTOR ARRAY−TYPE
CAMERA TUBE STRUCTURE) WEEngeler et al., Applied Physics Letters, Vol. 16, No. 5, March 1, 1970, "THE EPICON CAMERATUBE: AN
EPITAXIAL DIODE ARRAY VIDICON) Mr. SMBlumenfeld et al.
IEEE Transactions (IEEE Trans) Volume 1
ED18, No. 11, November 1971, and Engela (W.
E. Engeler), US Pat. No. 3,746,908. As disclosed in the references cited above, epitaxial deposition of single crystal silicon is well established in the semiconductor industry. For example, reaction temperature,
The influence of the composition of the deposition gas, gas flow rate, etc. on quality and deposition rate is well known.
It is already well known that single-crystal silicon nucleates well on a single-crystal substrate, but does not nucleate on polycrystalline or amorphous surfaces. Typically, a non-monocrystalline silicon film is deposited by placing a non-monocrystalline surface, such as the surface of a silicon dioxide layer, in an epitaxial deposition environment. Traditionally, forming single-crystal silicon on silicon dioxide has been accomplished by creating a lattice of single-crystal silicon islands, as described by Engela and Blumenfeld. This method relies on the movement of silicon atoms across the oxide surface between silicon islands to promote silicon island growth. If the migration distance of silicon that precipitates at a certain temperature is less than half the distance between the silicon islands, non-single crystal silicon nuclei will be formed on the oxide between the single crystal silicon islands. occurs. DISCLOSURE OF THE INVENTION In the course of research to provide a deposition method that prevents the formation of non-monocrystalline silicon layers and is not limited by epitaxial nucleation location geometry or growth time,
This inventive method has been discovered. In the method of the invention, a mask layer is formed on a semiconductor substrate, having at least one aperture that exposes a single crystal portion of the substrate. Silicon is then epitaxially deposited from a gas mixture containing a silicon source gas and a carrier gas. The substrate is then exposed to a gas mixture consisting of an etching gas and a carrier gas so that some of the silicon that has already been deposited is etched. This deposition and etching cycle is repeated an appropriate number of times to obtain a monocrystalline silicon layer of a predetermined size on the mask layer. [Embodiments of the Invention] Hereinafter, a detailed description will be given with reference to the drawings. As illustrated in FIG. 1, a substrate 10 having a substantially planar surface 12 is first provided. In the preferred embodiment, the material of the substrate 10 is single crystal silicon, and its surface 12 is a major crystal surface. However, as will be described later, the material of the substrate 10 is not limited to silicon. In a preferred embodiment, silicon dioxide (S _i
A perforated mask 14 consisting of an O ₂ ) layer is placed on the substrate surface 12.
form on top of. Silicon dioxide is chosen as the mask material because it is amorphous and can physically withstand subsequent epitaxial deposition steps. Furthermore, the S _i O ₂ mask 14 is easy to form and can be easily apertured using conventional photoetching techniques. However, the invention is not limited to the use of S _i O ₂ or only to the use of a mask of the specified thickness. mask 14
An important physical property of is that it is non-monocrystalline and can withstand the temperatures to which it is exposed during subsequent processing. Other suitable mask materials include, for example, silicon nitride and aluminum oxide. In FIG. 1, mask 14 has a plurality of apertures 16, the size, spacing and shape of which can vary. Further, although the embodiment shown in FIG. 1 shows a device having a plurality of apertures 16, the present invention is possible with just one aperture 16. This configuration with multiple apertures is for illustrative purposes only. The illustrated apertures 16 are, for example, square, circular, or striped. Substrate surface 12 exposed by each aperture 16
The part will be hereinafter referred to as "nucleation position 18". Nucleation location 18 in FIG. 1 can be positioned anywhere on surface 12. Nucleation location 18 in FIG. The only restriction is that each nucleation site 18 must be of single crystal structure. This is, for example, substrate 1
0 from a bulk single crystal material, providing a single crystal layer on the surface 12 of the originally non-single crystal substrate 10;
Alternatively, this can be accomplished by creating a polycrystalline surface 12 with grains sized such that each aperture 16 can fit completely within the boundaries of the grains. The masked structure of FIG. 1 is then processed in two steps: silicon deposition and etching cycles. In the first step, hereinafter referred to as the deposition step, silicon is deposited from a mixed gas containing a silicon source gas and a carrier gas. Furthermore,
A silicon etching gas may also be included in the gas mixture during this deposition step. In the second step, the etching step, a portion of the silicon deposited in the first step is etched in a mixture of silicon etching gas and carrier gas. This deposition and etching cycle is
This process is repeated as many times as necessary until a single crystal silicon layer of a predetermined size is formed on the mask layer 14. At each nucleation location 18, crystal growth will proceed generally lengthwise (perpendicular to surface 12) through the thickness of mask 14 and then laterally across the surface of mask 14. By repeating this cycle, an island 20 of single crystal silicon is finally formed at each nucleation location 18, as shown in FIG. This deposition and etching cycle (hereinafter referred to as deposition/etching) can be carried out in a conventional furnace at atmospheric or reduced pressure, and can be performed using various silicon source gases, silicon etching gases, etc. and carrier gas can be used. dichlorosilane as silicon source gas and HCl as etching gas (in both stages);
The table below summarizes various parameters for deposition/etching when hydrogen is used as the carrier gas.

Table These parameters were observed when the vertical growth rate was approximately 1.0 μ/min and the ratio of horizontal to vertical growth rate was 1.5. The vertical growth rate, the horizontal to vertical growth rate ratio, and the decision to use a silicon etch gas during the deposition cycle depend on the silicon source gas and its flow rate, the silicon etch gas and its flow rate, and the silicon etching gas and its flow rate. It varies as a function of deposition cycle time, etch cycle time, flow rate, furnace temperature, and deposition pressure. For example, if S _i H ₂ Cl ₂ is used as the silicon source gas, the flow rate of S _i H ₂ Cl ₂ can be varied between about 0.10 and 1.0 L/min and the silicon etching gas flow rate can be varied during the deposition step. By appropriately adjusting the flow rate, the longitudinal growth rate can be varied between about 0.4 and 2.0 μ/min. Lower reaction temperatures generally increase the horizontal to vertical growth rate ratio. For example, if the temperature in the furnace is changed from 1200°C to 1050°C using the parameters shown in the table above, the horizontal to vertical growth rate ratio will change between approximately 1.0 and 2.2. was observed. The effect of furnace temperature on growth rate and horizontal to vertical growth rate ratio also depends on the silicon used.
It depends on the source gas and deposition pressure. For example, S _i H ₄ can be deposited at a lower temperature than S _i H ₂ Cl ₂ ;
S _i Cl ₄ also allows deposition at higher temperatures than S _i H ₂ Cl ₂ . The deposition pressure can also vary, for example from about 100 Torr to atmospheric pressure. The deposition and etching times mentioned above can also be varied as a function of gas composition and temperature.
For example, the practical range of deposition times is approximately 30 seconds to 4 minutes, and the practical range of etching cycle times is approximately 20 seconds to 2 minutes. During the deposition stage of the deposition/etch stage described above, silicon is deposited from the silicon source gas on all exposed surfaces of the substrate and mask. The silicon deposited on each nucleation location 18 follows a single crystal lattice structure at that location. On the contrary, mask 14
The silicon deposited on top does not have a preferred orientation;
It is therefore deposited in the form of separated non-single crystal aggregates. Additionally, it has been determined that with the parameters described above, there is a certain time delay before non-single crystal deposition occurs on the mask, but single crystal silicon deposition begins immediately. Certain silicones, such as HCl, may be present during the deposition cycle.
If etching gas is present, mask 1 will be removed during deposition.
The possibility of non-monocrystalline silicon deposits occurring on 4 is reduced. During this deposition period, the relative amounts and deposition times of the silicon source gas and silicon etch gas are adjusted to maintain the ability to remove non-monocrystalline silicon deposited on mask 14 in subsequent etching steps. A balance must be struck to obtain a practical growth rate for single crystal silicon. The composition of the gas and the duration of the etching step in the deposition/etching step are determined to completely remove any non-single crystal aggregates remaining on the mask 14 after the deposition step. Although this etching also removes some of the single crystal silicon that has grown from the nucleation sites 18, the rate of dissolution of this single crystal silicon is considerably lower than that of the non-single crystal mass. Therefore, after one deposition/etch cycle, more silicon has been deposited during the deposition stage than is etched away during the etching stage, and this deposited material is essentially all monocrystalline. It is. Depending on the vertical to horizontal single crystal growth rate ratio obtained by the above-described deposition/etching method, a variety of useful semiconductor structures can be made. The structure shown in FIG. 2 can be used, for example, to form a plurality of individually selectively arranged semiconductor devices. Such a device includes, for example, a substrate 1
0 and silicon islands 20 can be made by selectively doping them using conventional semiconductor processing techniques. For example, the interface between each silicon island 20 and the substrate 10 can be made rectifying or non-rectifying by doping, and the internal doping distribution within each silicon island 20 and within the substrate 10 is Adjustments can be made using common photoetching techniques. 3 through 6 illustrate other structures that can be produced using the method of the invention. By successively applying the above-described deposition/etching method to the structure shown in FIG. 2, a plurality of silicon islands grow together and finally become continuous as shown in FIG. A single crystal silicon layer 22 is formed. FIG. 5 shows a structure similar to that of FIG. 3 with a monocrystalline silicon layer 22 formed on a mask 14 from a single nucleation site 18 exposed by a single aperture 16 in the mask 14. This shows that it can be manufactured. FIG. 4 shows another embodiment important in integrated circuit IC design. This is done by forming a cavity 24 by etching in a portion corresponding to the opening 16 in the silicon layer 22 shown in FIG.
It can be made. In this embodiment, the cavity 24 is
Through the entire thickness of the silicon layer 22 and the epitaxial silicon within each aperture 16, the substrate surface 1 is
2 is exposed. Therefore, if the size and shape of the opening 16 are designed in such a manner, a plurality of electrically isolated silicon island portions 26 can be formed. This type of structure is particularly useful in silicon-on-sapphire (SOS) applications where a plurality of single crystal silicon islands are formed on an insulating substrate. Additionally, depending on the application of the structure of FIG. 4, the cavity 24 in the structure can be subsequently filled with dielectric, resistive, or conductive material to create a planar structure. It can be seen that the structure of FIG. 4 can be similarly made from the single aperture structure of FIG. Also,
Similarly, a cavity may be provided in the structure of FIG. 2 or in a structure intermediate between the structures shown in FIGS. 2 and 3. FIG. 6 shows an example of a multi-level structure that can be manufactured according to the invention. Perforated mask 14
Separated monocrystalline silicon islands 26 are formed thereon by the deposition/etching method described above. Next, a perforated mask 2 is placed on this silicon island portion 26.
8 and then similarly epitaxially grown a second set of silicon islands 30 thereon. If desired, one or more cavities 24 can be provided to separate each silicon island 26 and/or each silicon island 30. In this way, multi-level integrated circuits with each level selectively separated, for example by a S _i O ₂ mask, can be made with the deposition/etching method of the present invention. This technology is expected to have a strong impact on the integration density and level of integration in future integrated circuits. It should be understood that the embodiments described above are merely illustrative and are not intended to limit the scope of the invention. A wide variety of single-level and multi-level structures can be made using this deposition/etching method.

[Brief explanation of drawings]

1 and 2 are diagrams showing an example of the processing sequence according to the present invention, and FIGS. 3 to 6 are diagrams each showing various structures manufactured by the method of the present invention. 10...Substrate, 12...Surface of substrate, 14...
mask layer, 16... opening, 18... nucleation position,
20...Single crystal silicon island.

Claims (1)

[Claims] 1. Preparing a semiconductor substrate having a single-crystal portion on the surface and a mask layer having openings on the single-crystal portion; The method includes the steps of depositing silicon and etching a portion of the deposited silicon in a gas mixture consisting of a silicon etching gas and a carrier gas, and repeating the deposition and etching cycle. A method of forming a single crystal silicon layer on a mask layer, the method comprising obtaining a single crystal silicon island extending from the substrate surface of the opening in the mask layer and overlapping the mask layer over a predetermined distance. .