JPS6214424A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS6214424A
JPS6214424A JP15357985A JP15357985A JPS6214424A JP S6214424 A JPS6214424 A JP S6214424A JP 15357985 A JP15357985 A JP 15357985A JP 15357985 A JP15357985 A JP 15357985A JP S6214424 A JPS6214424 A JP S6214424A
Authority
JP
Japan
Prior art keywords
metal film
film
electrode
electrode window
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15357985A
Other languages
Japanese (ja)
Inventor
Atsushi Sudo
淳 須藤
Kazunori Imaoka
今岡 和典
Shuji Tabuchi
修司 田渕
Shuichi Ohashi
修一 大橋
Yoshiaki Tanimoto
谷本 芳昭
Tsutomu Saito
勉 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15357985A priority Critical patent/JPS6214424A/en
Publication of JPS6214424A publication Critical patent/JPS6214424A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form a flattened electrode and to obtain a flat wiring by a method wherein growths of the metal film and etchings are alternately repeated and the electrode window to be opened on the insulating film is thus filled with the laminated metal film. CONSTITUTION:An electrode window 3 is opened on an insulating film 2 to be formed on an Si substrate 1. A metal film 10 is adhered inside the electrode window 3. The metal film 10 begins to grow on the insulating film 2 as well when the film thickness thereof becomes thicker in about 3,000Angstrom or more. At that point, the growth is stopped and the metal film 10 on the insulating film 2 is etched away by an ion milling method. A metal film 10 is again adhered in the electrode window 3. The metal film 10 on the insulating film 2 is etched away. Lastly the electrode window 3 is filled up with the metal film 10 to be grown. A wiring layer 11 is formed on the metal film 10. By this way, the flattened electrode is formed, thereby enabling to obtain a flat wiring.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置の製造方法に係り、そのうち、特に
電極の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an electrode.

ICなどの半導体装置は、高集積化されてきたため、多
数の素子を接続するための配線層が多層に形成されるよ
うになってきた。しかし、多層に積層するほど、基板面
では凹凸が激しく段差ができて、配線層の断線や短絡が
起こり易くなる欠点がある。
2. Description of the Related Art As semiconductor devices such as ICs have become highly integrated, multiple wiring layers have been formed to connect a large number of elements. However, the more layers are laminated, the more uneven the substrate surface becomes, and the disadvantage is that the surface of the substrate becomes more uneven and steps are formed, making it easier for disconnections and short circuits to occur in the wiring layers.

従って、現在、半導体基板の表面を平坦化することが重
要な課題となっているが、平坦化を阻害する大きな原因
に電極の形成があり、そのため、電極窓部分を平坦にす
る電極の形成方法が要望されている。
Therefore, flattening the surface of a semiconductor substrate is currently an important issue, but the formation of electrodes is a major cause of inhibiting flattening. is requested.

〔従来の技術と発明が解決しようとする問題点]第2図
(a)は従前の電極の形成方法を示す図で、1はシリコ
ン基板、2は二酸化シリコン(Si02)膜からなる絶
縁膜、3は電極窓、4は配線層(例えば、アルミニウム
膜)である。図のように、電極窓3にそのまま配線層4
を形成すると、電極窓部分で段差のために配線層が凹ん
で、その部分で断線を起こし易くなる。また、その上に
第2の配線層(図示せず)を形成する目的で、絶縁膜を
被着させると、その電極部分で絶縁膜が薄くなって、そ
の上に形成した第2の配線層と図中の配線層4とが短絡
し易い問題が起こる。
[Prior art and problems to be solved by the invention] FIG. 2(a) is a diagram showing a conventional method of forming an electrode, in which 1 is a silicon substrate, 2 is an insulating film made of silicon dioxide (Si02) film, 3 is an electrode window, and 4 is a wiring layer (for example, an aluminum film). As shown in the figure, the wiring layer 4 is directly attached to the electrode window 3.
If a wiring layer is formed, the wiring layer will be depressed due to the step at the electrode window portion, and wire breakage will easily occur at that portion. Furthermore, when an insulating film is deposited on top of the insulating film for the purpose of forming a second wiring layer (not shown), the insulating film becomes thinner at the electrode portion, and the second wiring layer formed thereon becomes thinner. A problem arises in that the wiring layer 4 in the figure is likely to be short-circuited.

従って、電極窓の平坦化について従前より色々な方法が
考案されており、例えば、最も汎用されている対策に、
電極窓部分で絶縁膜の肩を丸くして段差をなだらかにす
る方法がある。しかし、最近のように、高度に集積化さ
れ微細化されると、それだけでは十分ではなくなって、
積層するほど凹凸が激しくなる問題は解消せず、上記の
断線や短絡の危険性は増加してきた。その解決策として
、例えば、電極窓を埋没させる選択成長法などが検討さ
れている。
Therefore, various methods have been devised for flattening the electrode window. For example, the most widely used measures include:
One method is to round the shoulders of the insulating film at the electrode window part to make the difference in level gentle. However, as it has become more highly integrated and miniaturized in recent years, this alone is no longer sufficient.
The problem that the unevenness becomes more severe as the layers are stacked has not been resolved, and the risk of the above-mentioned wire breakage and short circuit has increased. As a solution to this problem, for example, a selective growth method in which the electrode window is buried is being considered.

選択成長法とは下地の材質によって選択的に成長膜が被
着する方法で、例えば、六弗化タングステン(WF6)
を熱分解させると、シリコン基板1上にのみタングステ
ン(W)が被着し、5i02膜2上には被着しないと云
う成長方法である。
The selective growth method is a method in which a grown film is selectively deposited depending on the underlying material.For example, tungsten hexafluoride (WF6)
This is a growth method in which when tungsten (W) is thermally decomposed, tungsten (W) is deposited only on the silicon substrate 1 and not on the 5i02 film 2.

しかし、このような選択成長方法は現在では、電極窓を
埋没するまで選択成長させることは難しく、選択成長の
膜厚は精々3000以上度で、それ以上は非選択的無差
別に被着し始める。従って、第2図(blに示すように
、タングステン膜5の上に配線層6を形成すると、段差
は幾分少なくなるが、上記例と同様に配線層は電極窓部
分で凹んで形成され、十分に平坦化することは難しい。
However, with such a selective growth method, it is currently difficult to selectively grow until the electrode window is buried, and the film thickness of selective growth is at most 3000 degrees or more, and beyond that, the film begins to be deposited non-selectively and indiscriminately. . Therefore, if the wiring layer 6 is formed on the tungsten film 5 as shown in FIG. It is difficult to achieve sufficient flatness.

また、第2図fc)に示すように、多結晶シリコンII
!J7を電極窓内にのみ選択成長させて埋没させ、その
上に配線層8を形成する電極配線の平坦化形成法が知ら
れている。塩素系反応ガス、例えば四塩化シリコン(S
iC14)やトリクロールシラン(SiHCl2 )を
熱分解して被着させると、5iO211!j!2の上に
は被着せず、シリコン基it上にのみ被着させ、その場
合は電極窓を多結晶シリコン膜で埋没させることができ
る。
In addition, as shown in Fig. 2 fc), polycrystalline silicon II
! A method of planarizing the electrode wiring is known, in which J7 is selectively grown and buried only in the electrode window, and the wiring layer 8 is formed thereon. Chlorine-based reactive gas, such as silicon tetrachloride (S
When pyrolyzed and deposited with iC14) or trichlorosilane (SiHCl2), 5iO211! j! In this case, the electrode window can be buried with a polycrystalline silicon film.

しかし、多結晶シリコン膜7をドープド多結晶シリコン
として導電性を与えても、その電気抵抗は比較的に高く
、微細デバイスの配線層として十分満足なものではない
However, even if the polycrystalline silicon film 7 is made of doped polycrystalline silicon to provide conductivity, its electrical resistance is relatively high, and it is not sufficiently satisfactory as a wiring layer of a microdevice.

本発明はこれらの問題点を除去した電極の平坦化形成法
を提案するものである。
The present invention proposes a flattening method for forming electrodes that eliminates these problems.

[問題点を解決するための手段] その問題は、絶縁膜を窓開けした電極窓内に、金属膜を
選択的に気相成長し、次いで、非選択的に被着した絶縁
膜上の該金属膜をエツチング除去し、かくして、該金属
膜の成長とエツチングとを交互に繰り換えして、前記電
極窓を金属膜で埋没させる工程が含まれている半導体装
置の製造方法によって解決される。
[Means for solving the problem] The problem is that a metal film is selectively grown in a vapor phase in an electrode window in which a window is opened in an insulating film, and then a metal film is grown in a vapor phase on the non-selectively deposited insulating film. The problem is solved by a method of manufacturing a semiconductor device, which includes the step of removing the metal film by etching, and then alternately repeating the growth and etching of the metal film to bury the electrode window with the metal film.

[作用] 即ち、金属膜が選択成長しなくなるまで被着させ、絶縁
膜上に被着し始めると、成長を中止して全面エツチング
して、絶縁膜を露出させる。このような成長とエツチン
グとの工程を繰り換えして、電極窓を埋没させる。
[Operation] That is, the metal film is deposited until it no longer selectively grows, and when it begins to deposit on the insulating film, the growth is stopped and the entire surface is etched to expose the insulating film. The electrode window is buried by repeating this growth and etching process.

そうすれば、電極と接続する配線層が平坦化され、基板
上で積層数を増やしても凹凸が増加しなくなる。
By doing so, the wiring layer connected to the electrode is flattened, and even if the number of laminated layers on the substrate is increased, the unevenness will not increase.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(al〜(e)は本発明にかかる電極形成工程順
断面図で、まず、同図(a)に示すように、シリコン基
板1上に形成した膜厚1μmの5i02膜2に、大きさ
1.5μm角の電極窓3が設けられている。
FIGS. 1A to 1E are sequential cross-sectional views of the electrode forming process according to the present invention. First, as shown in FIG. An electrode window 3 having a size of 1.5 μm square is provided.

次いで、第1図(blに示すように、膜厚3000人前
後のタングステン膜10を被着する。被着方法は化学気
相成長(CVD)法で、ヘリウム(He)などの中性ガ
スをキャリアガスとしてWF6ガスを導入し、それに水
素ガスを添加して、減圧気流中の数100℃の温度で熱
分解させる。反応式は次の通りである。
Next, as shown in FIG. 1 (bl), a tungsten film 10 with a thickness of about 3,000 layers is deposited.The deposition method is chemical vapor deposition (CVD) using a neutral gas such as helium (He). WF6 gas is introduced as a carrier gas, hydrogen gas is added thereto, and the mixture is thermally decomposed at a temperature of several hundred degrees Celsius in a reduced pressure air stream.The reaction formula is as follows.

WF6 +)i2−W+HF そうすると、タングステン膜10は電極窓3内のシリコ
ン基板にのみ被着するが、その膜厚を3000人程度以
上に厚くすると、もはや選択性が失われて、5i02膜
2の上にも成長し始めるが、その時点で成長を中止する
。この選択性が失われる原因は、その絶縁膜の表面状態
によるものと思われる。
WF6 +)i2-W+HF Then, the tungsten film 10 is deposited only on the silicon substrate within the electrode window 3, but when the film thickness is increased to about 3000 or more, the selectivity is lost and the tungsten film 10 is deposited only on the silicon substrate within the electrode window 3. It also begins to grow upwards, but at that point it stops growing. The reason for this loss of selectivity is thought to be due to the surface condition of the insulating film.

次いで、第1図(C)に示すように、5iO2P22上
に被着したタングステン膜IOをイオンミリング法でエ
ツチング除去する。それには、全面をイオンミリングし
て、5iO7膜上にタングステン膜がなくなった時点で
エツチングを中止する。所謂、コントロールエッチをお
こなうものである。そうして、更に、5i02膜を軽く
弗酸で工、チングして、表面状態を調整する。
Next, as shown in FIG. 1C, the tungsten film IO deposited on the 5iO2P22 is etched away by ion milling. To do this, the entire surface is ion-milled, and the etching is stopped when there is no more tungsten film on the 5iO7 film. This is what is called control etch. Then, the 5i02 film is further etched and etched with hydrofluoric acid to adjust the surface condition.

次いで、第1図(dlに示すように、再び上記の第1図
(blの工程を繰り換えして、再度タングステン[9!
10を被着させる。以降は、再び第1図(C1の工程を
繰り換えして、エツチングして5i02膜2上のタング
ステン1110を除去し、このような成長とエツチング
との工程を繰り換えして、最後に、第1図fe)に示す
ように、電極窓3の中をタングステン膜10で完全に埋
没させ、その上に配線層11を形成する。
Next, as shown in FIG. 1 (dl), the process in FIG. 1 (bl) above is repeated again, and tungsten [9!
10 is applied. Thereafter, the process shown in FIG. As shown in FIG. 1 (fe), the inside of the electrode window 3 is completely buried with a tungsten film 10, and a wiring layer 11 is formed thereon.

このようにすれば、配線層11は平坦化され、かくして
、基板上で多層配線を積層しても凹凸が増えることなく
、平坦な面に配線層が形成される。
In this way, the wiring layer 11 is flattened, and thus the wiring layer is formed on a flat surface without increasing unevenness even if multilayer wiring is stacked on the substrate.

[発明の効果] 以上の説明から明らかなように、本発明によれば平坦化
した電極が形成されて、平坦な配線が得られ、ICの信
頼性を向上させることができる効果があるものである。
[Effects of the Invention] As is clear from the above description, according to the present invention, flattened electrodes are formed, flat wiring can be obtained, and the reliability of the IC can be improved. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図1a)〜(e)は本発明にかかる電極の形成工程
順断面図、 第2図(aJ、 (bl、 (C1は従来の電極の形成
断面図である。 図において、 1はシリコン基板、   2はS+02膜、3は電極窓
、 4.6,8.11は配線層、 10はタングステン膜 第 11!1 6L未丙電&/1佑午逍I訂 fs 2 図
1a) to 1(e) are sectional views of the electrode according to the present invention in the order of forming steps, and FIG. 2 (aJ, (bl), (C1 is a sectional view of the conventional electrode formation process. Substrate, 2 is S+02 film, 3 is electrode window, 4.6, 8.11 is wiring layer, 10 is tungsten film

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜を窓開けした電極窓内に、金属膜を選択的に気相
成長し、次いで、非選択的に被着した絶縁膜上の該金属
膜をエッチング除去し、かくして、該金属膜の成長とエ
ッチングとを交互に繰り換えして、前記電極窓を金属膜
で埋没させる工程が含まれてなることを特徴とする半導
体装置の製造方法。
A metal film is selectively grown in a vapor phase in an electrode window in which an insulating film is opened, and then the metal film on the insulating film non-selectively deposited is removed by etching, thus growing the metal film. A method of manufacturing a semiconductor device, comprising the step of burying the electrode window with a metal film by alternately repeating and etching.
JP15357985A 1985-07-11 1985-07-11 Manufacture of semiconductor device Pending JPS6214424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15357985A JPS6214424A (en) 1985-07-11 1985-07-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15357985A JPS6214424A (en) 1985-07-11 1985-07-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6214424A true JPS6214424A (en) 1987-01-23

Family

ID=15565574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15357985A Pending JPS6214424A (en) 1985-07-11 1985-07-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6214424A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58120595A (en) * 1982-01-12 1983-07-18 ゼネラル・エレクトリック・カンパニイ Method of forming single crystalline silicon layer onto mask layer
JPS5944844A (en) * 1982-09-07 1984-03-13 Toshiba Corp Semiconductor device and manufacture thereof
JPS5972131A (en) * 1982-10-19 1984-04-24 Toshiba Corp Forming method for metal and metallic silicide film

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58120595A (en) * 1982-01-12 1983-07-18 ゼネラル・エレクトリック・カンパニイ Method of forming single crystalline silicon layer onto mask layer
JPS5944844A (en) * 1982-09-07 1984-03-13 Toshiba Corp Semiconductor device and manufacture thereof
JPS5972131A (en) * 1982-10-19 1984-04-24 Toshiba Corp Forming method for metal and metallic silicide film

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