JPS62205647A - Method of selectively depositing conductor material - Google Patents
Method of selectively depositing conductor materialInfo
- Publication number
- JPS62205647A JPS62205647A JP4902686A JP4902686A JPS62205647A JP S62205647 A JPS62205647 A JP S62205647A JP 4902686 A JP4902686 A JP 4902686A JP 4902686 A JP4902686 A JP 4902686A JP S62205647 A JPS62205647 A JP S62205647A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- layer
- tungsten
- deposited
- poly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000151 deposition Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 23
- 239000004020 conductor Substances 0.000 title claims description 11
- 239000000463 material Substances 0.000 title description 5
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 27
- 239000010937 tungsten Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 26
- 230000008021 deposition Effects 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims 3
- 239000012212 insulator Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 238000001020 plasma etching Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 4
- 239000011148 porous material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 241000989913 Gunnera petaloidea Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
Ｓ ｉ Ｏ２に設けられたコンタクトホール或いは層間
接続用のスルーホールを、タングステンで充填する場合
、反応性イオンエツチング（以下、ＲＩＥと略記）の異
方特性を利用して、開孔側面に多結晶シリコン（以下、
ポリＳｉ）層を残留被着せしめた後、化学気相成長法（
以下、ＣＶＤ法）によりタングステンを堆積する。成長
速度を小にすると、タングステンはポリＳｉ或いは単結
晶８１表面に選択的に堆積するのでコンタク１−＋、−
ルが速やかに充填される。[Detailed Description of the Invention] [Summary] When filling a contact hole provided in SiO2 or a through hole for interlayer connection with tungsten, the anisotropic characteristics of reactive ion etching (hereinafter abbreviated as RIE) Polycrystalline silicon (hereinafter referred to as
After residual deposition of the polySi layer, chemical vapor deposition (
Tungsten is deposited by CVD (hereinafter referred to as CVD method). When the growth rate is reduced, tungsten is selectively deposited on the surface of poly-Si or single crystal 81, so that contact 1-+,-
fills quickly.
本発明は半導体集積回路装置の製造に於いて、半導体基
板内の各種領域へのコンタクｌ一部あるいは層間接続部
を形成するための処理方法に関するもので、特にその開
口部をタングステンのような導電性材料で充填する方法
に関するものである。The present invention relates to a processing method for forming contact portions or interlayer connections to various regions within a semiconductor substrate in the manufacture of semiconductor integrated circuit devices. The present invention relates to a method of filling with a synthetic material.
近年集積回路の集積度が高まり、多層配線が採用される
に伴って、配線を接続すべき層間距離が大となる一方、
パターンの微細化により接続面積は小となっている。そ
のため、従来行われていたような、開口を設けて上層配
線層を被着するだけの方法では断線が生じやすく、良好
な接続が望めなくなる。そればかりでなく、表面の起伏
を増太さ仕、より上層の配線の形成に不利を招来するこ
とにもなる。In recent years, as the degree of integration of integrated circuits has increased and multilayer wiring has been adopted, the distance between layers to which wiring must be connected has become larger.
The connection area is becoming smaller due to the miniaturization of the pattern. Therefore, the conventional method of simply providing an opening and depositing an upper wiring layer tends to cause disconnection, making it impossible to expect a good connection. Not only that, but the undulations on the surface become thicker, which causes disadvantages in the formation of wiring in upper layers.
特に配線層をスパッタＡ！によって形成する場合、開口
部の狭い孔の底にＡＩが到達せず、良好な接続が得寵い
という問題がある。Especially the wiring layer with sputter A! In the case of forming the electrode by using the method described above, there is a problem that the AI does not reach the bottom of the hole with a narrow opening, making it difficult to obtain a good connection.
かかる不都合を避ける方法として、コンタクトホールヤ
スルーホールを導電体材料で充填しておき、その」−に
ＡＩ等の配線層を被着することによって、基板領域への
コンタクトや層間接続を形成することが行われている。As a method to avoid such inconvenience, it is possible to fill the contact hole or through hole with a conductive material and then deposit a wiring layer such as AI on the contact hole or through hole to form a contact to the substrate area or an interlayer connection. is being carried out.
この方法によれば」二層配線表面の起伏は僅かなものに
なり、配線を多層化するのに有利である。According to this method, the undulations on the surface of the two-layer wiring become slight, which is advantageous for multilayer wiring.
孔部に異種材料を充填する技術としては、孔部形成のた
めのエツチングマスク （例えばフォトレジスト）を利
用してリフトオフ処理を行う方法があるが、これはパタ
ーンが微細化した場合にも常に利用し得るというもので
はない。As a technique for filling holes with a different material, there is a method of performing a lift-off process using an etching mask (for example, photoresist) for hole formation, but this method is always used even when the pattern becomes finer. It's not something that can be done.
リフトオフによらない方法では、導電体材料、たとえば
ポリＳｉの堆積速度が下地材料の違いにより異なる点を
利用して、孔内に優先的に堆積させる方法が知られてい
る。As a method that does not rely on lift-off, a method is known in which a conductive material such as poly-Si is preferentially deposited in a hole by utilizing the fact that the deposition rate differs depending on the underlying material.
本発明に関連の深い技術として、タングステンの選択的
堆積法も公知である。これは単結晶Ｓｉ或いはポリＳｉ
の表面を５ｉ０２層で被覆し、部分的に３ｉ面を露出さ
せた状態で、ＣＶＤ法によってタングステンを堆積する
と、Ｓｉ表面に優先的にタングステンが堆積し、ＳｉＯ
□層表面には殆ど堆積しないというものである。A selective tungsten deposition method is also known as a technique closely related to the present invention. This is single-crystal Si or poly-Si.
When tungsten is deposited by the CVD method with the surface of the 5i02 layer covered with a 5i02 layer and the 3i plane partially exposed, tungsten is preferentially deposited on the Si surface, and the SiO
□There is almost no deposition on the surface of the layer.
このように下地によって堆積速度に大幅の差異を生ずる
理由は次のように考えられている。The reason why the deposition rate varies greatly depending on the substrate is thought to be as follows.
このＣＶＤ処理の原料は６弗化タングステンと水素であ
るが、被堆積面が３１の場合、最初に６弗化タングステ
ンがＳｉと反応して、気相の４弗化Ｓｉが発生すると共
にＳｉの表面にタングステン層が形成される。処理温度
を低くしてタングステンの還元速度を小に抑えると、こ
のタングステン層表面でのみ反応が進行し、Ｓ ｉ Ｏ
ｘ層表面にはタングステンの堆積がないという状態が実
現する。The raw materials for this CVD process are tungsten hexafluoride and hydrogen, but when the surface to be deposited is 31, tungsten hexafluoride first reacts with Si, generating Si tetrafluoride in the gas phase and A tungsten layer is formed on the surface. When the processing temperature is lowered to suppress the reduction rate of tungsten, the reaction proceeds only on the surface of this tungsten layer, resulting in S i O
A state is realized in which no tungsten is deposited on the surface of the x layer.
この技術によって、低結晶ＳｉあるいはポリＳｉ上のＳ
ｉ０２層に開口を設け、タングステンの選択的堆積によ
ってこれを充填しようとする場合、上記の事由により、
底面への堆積だけによって孔がｌｌｐめられていくので
、その進行は低速である。With this technology, S on low-crystal Si or poly-Si
If an opening is created in the i02 layer and attempted to be filled by selective deposition of tungsten, due to the above reasons,
Since the pores are filled only by deposition on the bottom surface, the progress is slow.
その他、本発明に用いられるＲＩＥが異方性であること
、それを利用して段差部のはソ垂直な側面に被エツチン
グ体を残留せしめる技術は、当業者には周知である。更
に、この種のエツチングが過度に進行するのを防止する
ため、被エツチング体とは異なる材質のエツチングスト
ッパを下敷きにしておくことも公知である。In addition, it is well known to those skilled in the art that the RIE used in the present invention is anisotropic, and that the technique of utilizing this to leave the object to be etched on the vertical side surfaces of the stepped portion is well known to those skilled in the art. Furthermore, in order to prevent this type of etching from proceeding excessively, it is also known to place an etching stopper made of a different material from that of the object to be etched.
既述したように、タングステンの選択成長によって開口
部を充填する方法は、処理速度が低い。As mentioned above, the method of filling the openings by selective growth of tungsten has a low processing speed.
選択的な堆積のためには反応速度が低いことが必要なの
で、これを高速化することは出来ない、また、深い孔を
充填しようとする場合、孔底への優先的堆積のみに依存
するのでは長時間の処理が必要になるが、処理時間が長
くなると５ｉＯｚ層」二にもタングステンが堆積する。Selective deposition requires a low reaction rate, which cannot be increased, and when trying to fill deep pores, it is difficult to rely solely on preferential deposition at the bottom of the pore. This requires a long processing time, but the longer the processing time, the more tungsten will be deposited on the 5iOz layer.
本発明の目的は、深さに比して口径が小である孔の内部
にタングステン等の導電体材料を高速に充填する方法を
提供することである。An object of the present invention is to provide a method for rapidly filling a conductive material such as tungsten into a hole whose diameter is small compared to its depth.
孔内部の導電体材料の堆積速度を向上することは、特許
請求の範囲の項に記載された本発明の方法によって可能
となるが、実施例に従ってこれを要約すると、ＲＹＥの
ような異方性のエツチングを利用してコンタクトホール
等の側面にポリＳｉ層を選択的に被着させ、タングステ
ンの堆積を孔の側面からも進行させることにより、孔を
高速に充填する。Increasing the deposition rate of conductor material inside the holes is possible by the method of the invention as described in the claims, but to summarize this according to the examples: By using etching, a poly-Si layer is selectively deposited on the side surfaces of a contact hole, etc., and the tungsten is deposited from the side surfaces of the hole, thereby filling the hole at high speed.
孔壁のポリＳｉ層は、底面の単結晶Ｓｔと同様に６弗化
タングステンと反応して、表面にタングステン層が形成
され、以後のタングステン堆積は水平面と同様に進行す
るので、底面からのみの堆積に比較して大幅に充填速度
が向上する。The poly-Si layer on the hole wall reacts with tungsten hexafluoride in the same way as the single-crystal St on the bottom surface, forming a tungsten layer on the surface, and subsequent tungsten deposition proceeds in the same way as on the horizontal surface. The filling rate is significantly increased compared to deposition.
第１図（ａｌ〜（ｄ＋は本発明の実施例の工程を示す模
式的断面図であり、以下、同図を参照しながら本発明を
説明する。FIG. 1 (al to (d+) are schematic cross-sectional views showing steps in an embodiment of the present invention, and the present invention will be described below with reference to the same figures.
同図ｆａｔはＳｉ層ｌの上にＳ ｉ Ｏｚ層２を被着し
、孔４を設けた状態を示す。孔４の底には薄いＳ ｉ
Ｏを層３が形成されているが、これは後のＲＩＥ工程で
ストッパとして働く皮膜であり、孔４を開けた後、軽く
酸化することによって形成される。The figure fat shows a state in which a SiOz layer 2 is deposited on a Si layer 1 and holes 4 are provided. At the bottom of hole 4 is a thin Si
An O layer 3 is formed, which is a film that acts as a stopper in the subsequent RIE process, and is formed by lightly oxidizing after opening the holes 4.
該皮膜３は本発明をより好適に実施するための補助的手
段であって実施要件ではない。５ｉＣｈ層２は層間絶縁
層の場合約１μｍの厚さであり、開孔の口径もは＼゛同
じ程度或いはそれ以下の場合が本発明の適用対象となる
。The film 3 is an auxiliary means for carrying out the present invention more preferably, and is not a requirement for carrying out the invention. The 5iCh layer 2 has a thickness of about 1 μm in the case of an interlayer insulating layer, and the present invention is applicable to cases where the diameter of the opening is about the same or smaller.
次いで、同図（ｂｌに示す如くポリＳｉ層５を堆積し、
ｒｌｌＨによってこれをエツチングする。ＲＩＥはは＼
垂直方向にのみ進行するので、垂直方向の厚さが大であ
る段差部にポリＳｉ５’が残留する。この状態が＋０１
図に示されている。Next, as shown in the same figure (bl), a poly-Si layer 5 is deposited,
Etch this by rllH. RIE haha\
Since it progresses only in the vertical direction, the poly-Si 5' remains in the stepped portion where the thickness in the vertical direction is large. This state is +01
As shown in the figure.
この処理は開花の側面にポリＳｉ層を形成することが目
的なので、始めに堆積するポリＳｉ層の厚さは、傾斜面
の作成を目的とする場合とは異なり、厚くする必要はな
い。むしろ残留するポリＳｉ壁が厚くなり過ぎないよう
、薄く形成することが望ましい。Since the purpose of this treatment is to form a poly-Si layer on the side surface of the flower, the thickness of the initially deposited poly-Si layer does not need to be thick, unlike when the purpose is to create a sloped surface. Rather, it is desirable to form the remaining poly-Si wall thin so that it does not become too thick.
ＲＩＥは孔の底部のＳｉＯ□薄層が露出するまで行われ
るが、本発明をより好適に実施するためには、＋０１図
に示されるようにや一オーバーにエツチングを行い、ポ
リＳｉ壁の上端が孔の上端よりも下がった状態とするの
が良い。RIE is performed until the thin layer of SiO□ at the bottom of the hole is exposed, but in order to better implement the present invention, etching is performed a little over one inch as shown in Figure +01 to remove the top edge of the poly-Si wall. It is preferable that the hole is lower than the top of the hole.
ポリＳｉ壁の上端が孔の上端とはソ一致する状態でタン
グステンを堆積すると、第２図に示すように、ポリＳｉ
上端から上方への堆積が進行し、不必要に盛り上がった
形状となることがあるので、それを回避するための処理
である。孔の底部にはエツチングストッパとしてＳ ｉ
ＯＺ薄層３が設けられているので、エツチングかや一
オーバーになっても差し支えない。When tungsten is deposited with the top of the poly-Si wall aligned with the top of the hole, the poly-Si
This process is to avoid the fact that the deposition progresses upward from the upper end, resulting in an unnecessarily raised shape. At the bottom of the hole, there is Si as an etching stopper.
Since the OZ thin layer 3 is provided, there is no problem even if the etching is slightly over-etched.
第１図に戻って、全面を軽くエツチングすることにより
孔底部のＳｉＯ□薄層を除去した後、ｆｄ１図の如く、
６弗化タングステンと水素を原料とし、処理温度は３０
０℃であるＣＶＤによってタングステン６を１１を積す
る。この場合、孔の底面と側面の両方でタングステンの
堆積が進行するので、孔部は速やかに充填されるが、Ｓ
ｉＯ□層２の上には堆積しない。Returning to Fig. 1, after removing the thin layer of SiO□ at the bottom of the hole by lightly etching the entire surface, as shown in Fig. fd1,
Tungsten hexafluoride and hydrogen are used as raw materials, and the processing temperature is 30
Tungsten 6 and 11 are deposited by CVD at 0°C. In this case, tungsten deposition progresses on both the bottom and side surfaces of the hole, so the hole is quickly filled, but S
It is not deposited on top of the iO□ layer 2.
この−ヒにＡｔ配線を形成すれば、断線がなく良好な層
間接続を持つ配線が形成される。If an At wiring is formed on this -H, a wiring with no disconnection and good interlayer connection will be formed.
以上説明したように、本発明によれば口径に比して深さ
が大である孔部に、速やかにタングステンを充填するこ
とができる。As explained above, according to the present invention, a hole whose depth is large compared to its diameter can be quickly filled with tungsten.
第１図は本発明の実施例の工程を模式的に示す断面図、
第２図は実施例の工程中の問題点を示す模式的断面図で
ある。
図において、
ｌは単結晶３ｉまたはポリＳ１．
２はＳ ｉ Ｏ２層、
３は薄いＳｉ０２層、
４はスルーホールまたはコンタク１ホール、５．５′は
ポリＳｉ、
６はタングステン
である。FIG. 1 is a sectional view schematically showing the process of an embodiment of the present invention, and FIG. 2 is a schematic sectional view showing problems in the process of the embodiment. In the figure, l is single crystal 3i or poly S1. 2 is a SiO2 layer, 3 is a thin Si02 layer, 4 is a through hole or contact hole, 5.5' is poly-Si, and 6 is tungsten.
Claims (4)
層を貫通する孔（４）を開け、 多結晶シリコン層（５）を堆積し、 異方性ドライエッチングを施して前記多結晶シリコン層
をエッチング除去すると共に、前記開孔の側壁に多結晶
シリコン層を残留せしめ、 しかる後、化学気相成長法によって、少なくも前記残留
多結晶シリコン層表面に、導電体材料（６）を堆積する
ことを特徴とする導電体材料の選択的堆積法。(1) A hole (4) passing through the insulator layer (2) formed on the semiconductor substrate is formed, a polycrystalline silicon layer (5) is deposited, and anisotropic dry etching is performed to form the above-mentioned While removing the polycrystalline silicon layer by etching, the polycrystalline silicon layer is left on the side wall of the opening, and then a conductive material (6) is deposited on at least the surface of the remaining polycrystalline silicon layer by chemical vapor deposition. ) is a selective deposition method for a conductive material.
体材料はタングステンであることを特徴とする特許請求
の範囲第１項記載の導電体材料の選択的堆積法。(2) The method for selectively depositing a conductive material according to claim 1, wherein the conductive material deposited on the surface of the residual polycrystalline silicon layer is tungsten.
シリコン層の上端が、前記開孔の上端よりも低くなるま
で実施することを特徴とする特許請求の範囲第１項また
は第２項記載の導電体材料の選択的堆積法。(3) The anisotropic dry etching is performed until the upper end of the residual polycrystalline silicon layer becomes lower than the upper end of the opening. selective deposition of conductive materials.
ドライエッチングに対してストッパとなる皮膜を形成し
ておくことを特徴とする特許請求の範囲第１項乃至第３
項記載の導電体材料の選択的堆積法。(4) A film serving as a stopper for the dry etching is formed directly under the insulating layer in which the through hole is formed.
Method for selectively depositing conductive materials as described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4902686A JPS62205647A (en) | 1986-03-06 | 1986-03-06 | Method of selectively depositing conductor material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4902686A JPS62205647A (en) | 1986-03-06 | 1986-03-06 | Method of selectively depositing conductor material |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62205647A true JPS62205647A (en) | 1987-09-10 |
Family
ID=12819590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4902686A Pending JPS62205647A (en) | 1986-03-06 | 1986-03-06 | Method of selectively depositing conductor material |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62205647A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4898841A (en) * | 1988-06-16 | 1990-02-06 | Northern Telecom Limited | Method of filling contact holes for semiconductor devices and contact structures made by that method |
-
1986
- 1986-03-06 JP JP4902686A patent/JPS62205647A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4898841A (en) * | 1988-06-16 | 1990-02-06 | Northern Telecom Limited | Method of filling contact holes for semiconductor devices and contact structures made by that method |
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