JP2001085515A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of high level integration, and its manufacturing method. SOLUTION: This semiconductor device is provided with a semiconductor element substrate 1 on which a semiconductor element is formed, a tapered trench part 5 which is formed in the substrate 1 and has opening wider than the bottom part, an isolation insulating film 3 formed by growing an insulating film over the whole surface of the substrate 1 containing the inside of the trench part 5, and a contact hole 6, which is formed in the isolation insulating film 3 on the substrate 1 and reaches the surface of the substrate 1. The thickness T of the isolation insulating film 3 on the substrate 1 is set smaller than the width D5 of the open part of the trench part 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an isolation insulating film formed by growing an insulating film on the surface of a semiconductor element substrate and in a trench, and formed on the isolation insulating film. And a method of manufacturing the same.

[0002]

2. Description of the Related Art First, a conventional example will be described. With the recent increase in the degree of integration of semiconductor devices, miniaturization of element isolation insulating films for separating element regions on a semiconductor element substrate has been regarded as important. As one of the methods therefor, as an element isolation insulating film having a trench structure in which a narrow groove (hereinafter, referred to as a trench) is formed in a semiconductor element substrate and an insulating film is buried in the trench (hereinafter, referred to as isolation insulation). (Referred to as membrane). This isolation insulating film can insulate and isolate the element regions to a deep position in the semiconductor element substrate. Therefore, there is an advantage that the insulation isolation characteristics are higher than the element isolation by the LOCOS method (local oxidation method) which is one of the conventional methods.

[0003] In particular, SOI (Silicon On Ins) having a laminated structure of a semiconductor element substrate and an intermediate insulating layer.
In the case where the above-described isolation insulating film is applied to a substrate, if the lower end of the isolation insulating film is formed so as to reach the intermediate insulating layer existing in the middle of the SOI substrate, the isolation insulating film and the intermediate insulating layer And can be completely insulated and separated. Therefore, according to such a method, a structure having extremely high insulation isolation characteristics can be obtained between the element regions.

Here, FIG. 3 is an explanatory view showing basic steps of a conventional method for manufacturing a semiconductor device.

FIG. 3A shows an SOI substrate 107 having a laminated structure of a supporting substrate 102, an intermediate insulating layer 104 and a semiconductor element substrate 101. In the SOI substrate 107, in order to form the trench 105 in the semiconductor element substrate 101, a resist mask covering the isolation region is formed on the surface of the semiconductor element substrate 101, and the resist mask is used to form the semiconductor element substrate 101. Anisotropic etching is performed on the surface (not shown). After this step, a trench 105 reaching the intermediate insulating layer 104 is formed as shown in FIG.

Next, an insulating film made of a silicon oxide film or the like is formed on the entire surface of the semiconductor element substrate 101 including the trench 105 by a chemical vapor deposition method or the like.
5 is grown to be thicker than the width of the opening 5 to form an isolation insulating film 103 as shown in FIG.

Subsequently, in the isolation insulating film 103 grown on the surface of the semiconductor element substrate 101, a contact hole 106 reaching the surface of the semiconductor element substrate 101 as shown in FIG. Formed. Thereafter, predetermined electric wiring is formed.

Further, the isolation insulating film 103 is formed in the trench 105.
In the step of growing, in order to prevent generation of voids in the trench 105, the angle formed by each surface inside the trench 105 with respect to the bottom surface is 88 degrees or less, and
Non-doped silicate glass (NS) grown by low pressure chemical vapor deposition with a low growth rate
G) is being studied.

[0009]

However, in the conventional example described above, in the step of growing an insulating film over the entire surface of the semiconductor element substrate 101 including the trench 105,
If the thickness of the isolation insulating film 103 after the growth is reduced, a depression occurs on the surface of the isolation insulating film 103 on the trench 105. The dent may cause disconnection in a later step of forming an electric wiring. For this reason, in order to eliminate the occurrence of the depression, the thickness of the isolation insulating film 103 after the growth is made larger than the width of the opening of the trench 105. That is, the minimum thickness of the isolation insulating film 103 after growth has been determined depending on the width of the opening of the trench 105.

Here, when a higher isolation breakdown voltage is required in the element isolation breakdown voltage of the isolation insulating film 103, it is necessary to increase the width of the opening of the trench 105. Accordingly, as described above, it is necessary to increase the minimum thickness of the isolation insulating film 103 after the growth.

As a result, the subsequent contact hole 106
In the process of forming and wiring. That is, as the width of the trench 105 increases, the thickness of the isolation insulating film 103 after growth increases. Therefore,
Contact hole 10 provided on the surface of semiconductor element substrate 101
6 has an increased aspect ratio. Here, the width of the opening of the contact hole 106 has to be increased according to the thickness of the isolation insulating film 103 due to the manufacturing limit of the aspect ratio. Therefore, there has been a disadvantage that the degree of integration of the element is increased and the integration is increased.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which can solve the above-mentioned disadvantages of the prior art, and which can provide a highly integrated semiconductor device and a method of manufacturing the same.

[0013]

In order to achieve the above-mentioned object, in each of the semiconductor devices according to the present invention, a semiconductor element substrate on which a semiconductor element is formed and a semiconductor element substrate are provided. A tapered groove having a wider opening than the bottom; a separation insulating film formed by growing an insulating film over the entire surface of the semiconductor element substrate including the inside of the groove; And a contact hole reaching the surface of the semiconductor element substrate.
A common feature is that the thickness of the isolation insulating film on the semiconductor element substrate is smaller than the width of the opening of the groove. As a result, the aspect ratio of the contact hole can be reduced, and the width of the opening can be reduced, thereby increasing the possibility of high integration.

Further, the above-mentioned isolation insulating film may be made of non-doped silicate glass grown by a low pressure chemical vapor deposition method. It may have a laminated structure with non-doped silicate glass. Further, the present invention can be applied to a case where the above-described semiconductor element substrate is a single crystal silicon substrate.

Further, in the method of manufacturing a semiconductor device according to any one of claims 5 to 10, a groove forming step of forming a tapered groove in which the width of the opening is wider than the bottom in the semiconductor element substrate; An insulating film is grown on the entire surface of the semiconductor element substrate including the inside of the groove formed in the step by a low pressure chemical vapor deposition method so as to be at least thicker than the width of the opening of the groove to form an isolation insulating film. An insulating film forming step; and a contact hole forming step of forming a contact hole reaching the surface of the semiconductor element substrate in the isolation insulating film on the semiconductor element substrate grown in the isolation insulating film forming step. In addition, between the isolation insulating film forming step and the contact hole forming step, an isolation insulating film etching step of etching the isolation insulating film grown in the isolation insulating film forming step to a desired thickness by anisotropic plasma etching is provided. That is a common feature.

This eliminates the occurrence of depressions on the surface of the isolation insulating film grown in the isolation insulating film forming step, and can further flatten the surface shape. In addition, by performing the etching, the aspect ratio at the time of forming the contact hole can be reduced.
The width of the opening of the contact hole can be reduced, and the possibility of high integration increases. Also, by making the thickness of the isolation insulating film after being etched in the isolation insulating film etching step smaller than the width of the opening of the groove,
The width of the opening of the contact hole can be further reduced.

Here, the isolation insulating film grown in the isolation insulating film forming step may be formed of non-doped silicate glass. Regarding this isolation insulating film, besides, a high-temperature oxide film,
On this, a non-doped silicate glass may be used to form a laminated structure. Further, traethyl orthosilicate may be used instead of non-doped silicate glass. Further, the present invention can be applied to a case where the above-described semiconductor element substrate is formed of a single crystal silicon substrate.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. Here, FIG. 1 is a schematic sectional view of a semiconductor device showing an embodiment of the present invention.

The semiconductor device shown in FIG. 1 has a structure in which a supporting substrate 2 having an arbitrary thickness and an intermediate insulating layer 4 made of a silicon oxide film having a thickness of about 2 μm are formed on a supporting substrate 2 having a thickness of 5 μm. An SOI substrate 7 is formed by laminating semiconductor element substrates 1 each composed of a single-crystal silicon substrate having a thickness of about 1 nm.

On the surface of the semiconductor element substrate 1, a trench 5 is formed so as to reach the intermediate insulating layer 4. In addition, the angle α formed between each inner surface of the trench 5 and the bottom surface is formed to be 88 degrees or less. Here, the width D5 of the opening of the trench 5 is determined by the required element isolation breakdown voltage. For example, 200
Trench 5 in case of required value of element isolation breakdown voltage of [V]
The width D5 of the opening is about 2 μm, and also in this embodiment, D5 is 2 μm.

On the surface of the semiconductor element substrate 1 including the trench 5, an isolation insulating film 3 is formed by growing non-doped silicate glass (NSG) by low pressure chemical vapor deposition. The isolation insulating film 3 has a laminated structure in which a non-doped silicate glass is laminated by a low pressure chemical vapor deposition method on an upper layer obtained by growing a high temperature oxide film (HTO) by a low pressure chemical vapor deposition method. Is also good. Here, in the present embodiment, the thickness T of the isolation insulating film 3 formed on the surface of the semiconductor element substrate 1 described above is about 1 μm.

Further, the isolation insulating film 3 on the semiconductor element substrate 1
A contact hole 6 reaching the surface of the semiconductor element substrate 1 is formed. Here, for high integration, the width D6 of the opening of the contact hole 6 is about 0.5 μm. Also in this case, the aspect ratio (that is, T / D6) of the contact hole 6 is about 2, which is a range in which the manufacturing can be sufficiently performed. Therefore, it is possible to realize a semiconductor device in which the width D6 of the opening of the contact hole 6 is small, that is, the degree of integration of elements is high.

Further, in the above-described embodiment, the supporting substrate 2
And a case where the present invention is applied to an SOI substrate 7 having a laminated structure of the intermediate insulating layer 4 and the semiconductor element substrate 1, but the present invention is not particularly limited to this SOI substrate 7. The semiconductor element substrate 1 can be applied to various substrates other than the single crystal silicon substrate.

Next, a method for manufacturing the above-described semiconductor device will be described with reference to FIG. Here, FIG. 2 is an explanatory diagram of a basic process of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2A shows a structure in which a supporting substrate 2 having an arbitrary thickness and an intermediate insulating layer 4 made of a silicon oxide film having a thickness of about 2 μm are formed on the supporting substrate 2.
An SOI substrate 7 is formed by stacking semiconductor element substrates 1 each formed of a single-crystal silicon substrate having a thickness of about μm.

Here, a resist mask (not shown) covering the isolation region is formed on the surface of the semiconductor element substrate 1, and anisotropic etching is performed using this resist mask. Thereafter, the above-described resist mask is removed, and FIG.
A trench 5 is formed to reach the intermediate insulating layer 4 as shown in FIG. Here, the angle α formed between each surface inside the trench 5 and the bottom surface is
Is 88 degrees or less. By doing so, it is possible to prevent generation of voids in the trench 5 in a step of growing an insulating film into the trench 5 described later. The width D5 of the opening of the trench 5 is determined by the required element isolation breakdown voltage. For example, 200
Trench 5 in case of required value of element isolation breakdown voltage of [V]
The width D5 of the opening needs to be about 2 μm.

Subsequently, in FIG. 2C, the trench 5
A non-doped silicate glass (NSG) as an insulating film is grown on the surface of the semiconductor element substrate 1 including the silicon nitride by a low-pressure chemical vapor deposition method having a low growth rate to form an isolation insulating film 3 (isolation insulating film formation). Process). Here, the isolation insulating film 3 may have a laminated structure in which non-doped silicate glass is laminated by a low pressure chemical vapor deposition method on an upper layer obtained by growing a high temperature oxide film (HTO) by a low pressure chemical vapor deposition method. Further, traethyl orthosilicate (TEOS) may be used instead of the non-doped silicate glass. Here, when the width D5 of the opening of the trench 5 is about 2 μm, the thickness T ′ of the grown isolation insulating film 3 also needs to be about 2 μm. If the thickness T ′ is small, a depression is formed at the center of the isolation insulating film 3 on the trench 5. The thickness T ′ of the isolation insulating film 3 needs to be at least larger than the width D5 of the opening of the trench 5. As described above, the isolation insulating film 3 having a sufficient thickness
Is grown and buried in the trench 5 to flatten the surface shape of the isolation insulating film 3.

After the above-described steps, an isolation insulating film 3 of about 2 μm is grown on the entire surface of the semiconductor element substrate 1. Subsequently, as shown in FIG. 2D, the surface of the isolation insulating film 3 grown on the surface of the semiconductor element substrate 1 by anisotropic oxide film plasma etching predominant in the direction perpendicular to the surface of the semiconductor element substrate 1. The whole is uniformly etched to reduce the thickness T of the isolation insulating film 3 (isolation insulating film etching step). For example, the thickness (T ′ in FIG. 2C)
The isolation insulating film 3 grown to about 2 μm is
Etching is performed until the thickness (T in FIG. 2D) of the isolation insulating film 3 in which is easily formed becomes about 1 μm. here,
The above-mentioned etching method is not limited to only the anisotropic oxide film plasma etching, but may be another etching method.

Then, as shown in FIG. 2E, a contact hole 6 is formed using a known technique such as etching (contact hole forming step). Here, even when the width D6 of the opening of the contact hole 6 is set to 0.5 μm, the aspect ratio of the contact hole 6 (that is, T / D6) is about 2, which is a range in which a sufficient manufacturing is possible. . Therefore, it is possible to realize a semiconductor device in which the width D6 of the opening of the contact hole 6 is small, that is, the degree of integration of elements is high.

In the above-described manufacturing method of the present embodiment, specific numerical values have been described, but the numerical values are not limited. For example, if the thickness T of the isolation insulating film 3 is etched to about 0.5 μm, the width D6 of the opening of the contact hole 6 can be further reduced as a matter of course. Therefore, it is possible to provide a semiconductor device having a higher element integration degree and a method for manufacturing the same.

Further, in the above-described embodiment, the supporting substrate 2
And a case where the present invention is applied to an SOI substrate 7 having a laminated structure of the intermediate insulating layer 4 and the semiconductor element substrate 1, but the present invention is not particularly limited to this SOI substrate 7. The semiconductor element substrate 1 can be applied to various substrates other than the single crystal silicon substrate.

[0032]

As described above, according to the present invention,
By growing the isolation insulating film thicker than the width of the opening of the trench in the isolation insulating film forming step, the surface of the isolation insulating film on the trench can be formed to have a flat surface shape without depression. Thus, it is possible to prevent a step of forming the electric wiring and disconnection of the formed electric wiring. Further, even when a high withstand voltage is required for the isolation voltage of the isolation insulating film and the width of the opening of the trench needs to be increased, the entire surface of the isolation insulating film grown thick on the semiconductor element substrate is etched. Accordingly, it is possible to make the contact hole have a required thickness that is easy to manufacture. Thus, even if the width of the opening of the contact hole is reduced in the step of forming the contact hole, the aspect ratio can be easily set to a range that can be manufactured. That is,
It is possible to increase the degree of integration of elements for manufacturing a highly integrated semiconductor device, and it is possible to provide an unprecedented excellent semiconductor device and a manufacturing method thereof.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing basic steps of a method for manufacturing a semiconductor device, which is an embodiment of the present invention.

FIG. 3 is an explanatory view showing basic steps of a method of manufacturing a semiconductor device, which is a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor element substrate 2 Support substrate 3 Separation insulating film 4 Intermediate insulating layer 5 Groove (trench) 6 Contact hole 7 SOI substrate

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (10)

[Claims] A semiconductor element substrate on which a semiconductor element is formed; a tapered groove provided in the semiconductor element substrate, wherein an opening is wider than a bottom; and a semiconductor element substrate including the inside of the groove. A semiconductor device comprising: an isolation insulating film formed by growing an insulating film over the entire surface; and a contact hole reaching the surface of the semiconductor element substrate in the isolation insulating film on the semiconductor element substrate. Wherein the thickness of the isolation insulating film is smaller than the width of the opening of the groove. 2. The semiconductor device according to claim 1, wherein said isolation insulating film is made of non-doped silicate glass grown by a low pressure chemical vapor deposition method. 3. The semiconductor device according to claim 1, wherein said isolation insulating film has a laminated structure of a high-temperature oxide film grown by low pressure chemical vapor deposition and non-doped silicate glass. 4. The semiconductor device according to claim 1, wherein said semiconductor element substrate is a single crystal silicon substrate. 5. A groove forming step of forming a tapered groove in which a width of an opening is wider than a bottom in a semiconductor element substrate, and a step of forming a groove on the surface of the semiconductor element substrate including the inside of the groove formed in the groove forming step. An isolation insulating film forming step of forming an isolation insulating film by growing an insulating film thicker than at least the width of the opening of the groove by low-pressure chemical vapor deposition over the entire surface, and forming the isolation insulating film. A method of manufacturing a semiconductor device, comprising: a contact hole forming step of forming a contact hole reaching a surface of a semiconductor element substrate in a grown isolation insulating film on a semiconductor element substrate; And an isolation insulating film etching step of etching the isolation insulating film grown in the isolation insulating film forming step to a desired thickness by anisotropic plasma etching. Manufacturing method of a semiconductor device. 6. The semiconductor device according to claim 5, wherein a thickness of the isolation insulating film after being etched in the isolation insulating film etching step is smaller than a width of an opening of the groove. Production method. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the isolation insulating film grown in the isolation insulating film forming step is formed of non-doped silicate glass. 8. The isolation insulating film grown in the isolation insulating film forming step is formed in a laminated structure of a high-temperature oxide film and a non-doped silicate glass thereon. Of manufacturing a semiconductor device. 9. Instead of the non-doped silicate glass,
9. The method for manufacturing a semiconductor device according to claim 7, wherein triethyl orthosilicate is used. 10. A semiconductor device according to claim 5, wherein said semiconductor element substrate is formed of a single crystal silicon substrate.
Or a method for manufacturing a semiconductor device according to item 9.