JP2003282707A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same in which a manufacturing yield is improved. <P>SOLUTION: The method of manufacturing the semiconductor device comprises a process (a) to form a first insulation layer 20, a process (b) to form a second insulation layer on the first insulation layer 20, a process (c) to form a mask layer R1 including a predetermined pattern on the second insulation layer, a process (d) to form a through-hole 50 by etching the first insulation layer 20 and the second insulation layer 30, and a process (e) to side-etch the first insulation layer 30 and the second insulation layer 30 in the through-hole 60, wherein the process (e) is performed under the condition that the etching rate of the second insulation layer 30 is higher than that of the first insulation layer 20. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

BACKGROUND ART A semiconductor device generally has a plurality of wiring layers. An interlayer insulating layer is provided between the wiring layers, and a contact layer is provided in the interlayer insulating layer to electrically connect the wiring layers to each other. This contact layer is generally formed by forming a through hole in the interlayer insulating layer and filling the through hole with a conductive material.

A technique has been proposed in which the diameter of the upper portion of the through hole is made larger than that of the lower portion in order to facilitate the filling of the conductive material in the through hole. Such a through hole can be formed by isotropically etching the upper part of the interlayer insulating layer and then anisotropically etching the interlayer insulating layer (for example, JP-A-9-36101).

An object of the present invention is to provide a semiconductor device having an improved yield and a manufacturing method thereof.

[0005]

[Means for Solving the Problems]

1. 1. Method of Manufacturing Semiconductor Device 1.1 Method of Manufacturing First Semiconductor Device A method of manufacturing a first semiconductor device of the present invention comprises (a) a step of forming a first insulating layer, and (b) a step of forming the first insulating layer. A step of forming a second insulating layer thereon, (c) a step of forming a mask layer having a predetermined pattern on the second insulating layer,
(D) a step of etching the first insulating layer and the second insulating layer using the mask layer as a mask to form a through hole, and (e) the first insulating layer and the second hole in the through hole. The step (e) is performed under the condition that the etching rate of the second insulating layer is faster than the etching rate of the first insulating layer.

According to the present invention, the following operational effects can be achieved, for example. The step (e) is performed under the condition that the etching rate of the second insulating layer is faster than the etching rate of the first insulating layer. Therefore, after the step (e),
The diameter of the through hole in the second insulating layer is larger than the diameter of the through hole in the first insulating layer. Therefore,
It is possible to form a through hole in which a conductive material can be easily embedded.

Further, since the through hole is formed in the step (d) before the step (e), the through hole can be surely formed in a predetermined region.

From the above, according to the first semiconductor device manufacturing method of the present invention, the yield can be improved.

In the present invention, the first insulating layer is a silicon oxide layer containing boron and phosphorus, and the second insulating layer is
A silicon oxide layer formed by reacting an organosilane compound with a compound containing oxygen can be formed. Thereby, the step (e) can be carried out by using, for example, hydrofluoric acid as an etching solution.

1.2 Second Method for Manufacturing Semiconductor Device A second method for manufacturing a semiconductor device according to the present invention comprises (a) a step of forming an interlayer insulating layer, and (b) a predetermined process on the interlayer insulating layer. Forming a mask layer having a pattern of (c)
Etching the interlayer insulating layer using the mask layer as a mask to form a through hole, and (d)
A step of side-etching the interlayer insulating layer in the through hole is included, and the step (d) is performed under a condition that an etching rate of an upper portion of the interlayer insulating layer is faster than an etching rate of a lower portion of the interlayer insulating layer.

According to the present invention, the following operational effects can be obtained, for example. The step (d) is performed under the condition that the etching rate of the upper portion of the interlayer insulating layer is faster than the etching rate of the lower portion. Therefore, after the step (d),
The diameter of the through hole in the upper part of the interlayer insulating layer is larger than the diameter of the through hole in the lower part of the interlayer insulating layer.
Therefore, it is possible to form the through hole in which the conductive material is easily embedded.

Since the through hole is formed in the step (c) before the step (d), the through hole can be surely formed in a predetermined region.

From the above, according to the second method of manufacturing a semiconductor device of the present invention, the yield can be improved.

In the present invention, the interlayer insulating layer is composed of a silicon oxide layer containing boron and phosphorus, and the boron concentration of the silicon oxide layer can be made thinner on the upper layer side than on the lower layer side. This makes it possible to form a through hole having a diameter that gradually decreases from the top to the bottom, making it easier to embed the conductive material. This is because the lower the boron concentration, the faster the etching rate of the interlayer insulating layer.

In the present invention, the interlayer insulating layer is formed by laminating a plurality of insulating layers, and the step (d) can be performed under the condition that the etching rate becomes higher toward the upper insulating layer. .

2. Semiconductor Device 2.1 First Semiconductor Device A first semiconductor device of the present invention includes an interlayer insulating layer having a through hole, wherein the interlayer insulating layer is composed of a silicon oxide layer containing boron and phosphorus, The boron concentration of the insulating layer is thinner on the upper layer side than on the lower layer side.

In the present invention, the diameter of the through hole may be larger on the upper layer side than on the lower layer side.

2.2 Second Semiconductor Device A second semiconductor device of the present invention includes an interlayer insulating layer having a through hole, and the interlayer insulating layer includes a first silicon oxide layer containing boron and phosphorus, A second silicon oxide layer containing boron and phosphorus provided on the first silicon oxide layer, wherein the concentration of boron in the second silicon oxide layer is boron in the first silicon oxide layer. Less than the concentration of.

In the present invention, the diameter of the through hole in the second silicon oxide layer can be made larger than the diameter of the through hole in the first silicon oxide layer.

The semiconductor device according to the present invention is not limited to a semiconductor integrated circuit, and transistors or wirings are formed on a substrate and include, for example, a liquid crystal display.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

1. Method for Manufacturing Semiconductor Device A method for manufacturing a semiconductor device according to the embodiment will be described with reference to FIGS.

First, as shown in FIG. 1A, the wiring layer 1
The BPSG layer 20 is formed on the substrate 10 on which the 2 is provided. The BPSG layer 20 is formed, for example, by vapor-phase growing a silane compound (for example, silane), oxygen, ozone, and the like, and a gas containing phosphorus and boron.

Next, as shown in FIG. 1B, the BPSG layer 20 is planarized by annealing at 800 to 900 ° C. in a nitrogen atmosphere. That is, the BPSG layer 20 is reflowed at a high temperature.

Next, as shown in FIG. 2A, BPSG
On the layer 20, an organic silane compound is reacted with a compound containing oxygen (for example, oxygen, ozone, N ₂ O) to give T
An EOS-based silicon oxide layer 30 is formed. Examples of the organic silane compound include tetraethoxysilane (tetrae
thoxysilane), tetramethoxysilane
lane) and tetramethylsilane. As a forming method, for example, a plasma chemical vapor deposition (CVD) method can be mentioned.
The formation temperature is, for example, 300 to 500 ° C. As a result, the BPSG layer 20 and the TEOS-based silicon oxide layer 3
An interlayer insulating layer 40 of 0 and 0 is formed. The thickness of the interlayer insulating layer 40 is, for example, 800 to 1000 nm. The thickness of the TEOS-based silicon oxide layer is determined in consideration of the shape of the through hole to be obtained.

Next, a resist layer R1 having a predetermined pattern is formed on the TEOS type silicon oxide layer 30.

Next, as shown in FIG.
Anisotropically etch the interlayer insulating layer 40 using the layer R1 as a mask
To form a through hole 60. This etching
Can be performed using a known etching method,
For example, a dry etching method can be used.
A specific example of the dry etching method is reactive
Ion etching, inductively coupled plasma etching, E
CR plasma etching can be mentioned. Etch
Etching the interlayer insulating layer 40
The gas is not particularly limited as long as it is capable of
(Eg CHF ₃, CF_Four) Containing gas
it can.

Next, as shown in FIG. 3A, the TEOS type silicon oxide layer 30 and the BPSG layer 20 in the through hole 60 are side-etched. This etching is performed under the condition that the etching rate of the TEOS-based silicon oxide layer 30 is faster than the etching rate of the BPSG layer 20. Specifically, when side etching is performed using hydrofluoric acid or a solution of hydrofluoric acid and a buffer solution as an etching solution, the etching rate of the TEOS-based silicon oxide layer 30 can be made faster than the etching rate of the BPSG layer 20. As a result, after etching, the holes 6 in the TEOS-based silicon oxide layer 30 are removed.
The diameter of 2 is larger than the diameter of the hole 64 in the BPSG layer 20. As a result, in the subsequent process, the through hole 60
It becomes easy to embed a conductive material in the.

Further, in this etching process, even if the etching solution permeates the interface between the TEOS type silicon oxide layer 30 and the resist layer R1 and the resist layer is lifted off, the through hole 60 is first formed. Therefore, the problem as in the comparative example described later does not occur. That is,
The through hole 60 can be surely formed in a desired area.

Next, after removing the resist layer R1, FIG.
As shown in (B), the contact layer 70 is formed in the through hole 60. The contact layer 70 is formed, for example, by filling the through hole 60 with a conductive material and etching back the conductive material. Examples of the conductive material include tungsten, aluminum, aluminum alloys, copper, and copper alloys. Examples of the method of filling the hole with the conductive material include a CVD method, a PVD method, and a plating method.

2. Effect Hereinafter, the function and effect of the embodiment will be described.

(1) In the above embodiment, the interlayer insulating layer 40 is anisotropically etched to form the through hole 60, and then the interlayer insulating layer 40 in the through hole 60 is side-etched. This side etching process is
The etching rate of the TEOS-based silicon oxide layer 30 is
The etching rate is higher than the etching rate of the BPSG layer 20. Therefore, the upper portion of the through hole 60 (TE
The diameter of the hole 62 in the OS-based silicon oxide layer can be made larger than the diameter (hole in the BPSG layer) 64 below the through hole 60. As a result, the conductive material is easily embedded in the through hole 60.

Further, even if the resist layer R1 is peeled or displaced in the side etching step of the interlayer insulating layer 40, the through hole 60 is already formed. Therefore, the through hole is formed in a desired region. The problem of becoming difficult does not arise. That is, according to the present embodiment, it is possible to form the through hole 60 in which the conductive material is easily embedded, and it is possible to reliably form the through hole 60 in a desired region. Therefore, the yield can be improved.

(2) In this method of manufacturing a semiconductor device, a device having a high formation density of through holes, for example, a power source I is used.
It is useful for manufacturing C, memory, and driver. This is because if the formation density of the through holes is high, the problem of the comparative example that occurs when forming the through holes, that is, the resist layer is easily peeled off or displaced.

3. Semiconductor Device A semiconductor device formed by the above semiconductor device manufacturing method has, for example, the following configuration.

As shown in FIG. 3B, the interlayer insulating layer 40
Is a first insulating layer (BPSG layer) 20 and a second insulating layer (TE
OS-based silicon oxide layer) 30. Interlayer insulation layer 40
A through hole 60 is provided in the. The diameter of the upper portion 62 of the through hole 60 is equal to that of the lower portion 64 of the through hole 60.
Larger than the diameter of.

4. Comparative Example After the upper portion of the interlayer insulating layer 130 is isotropically etched using the resist layer R2 as a mask as shown in FIG. 5A, the interlayer insulating layer 130 is anisotropically etched as shown in FIG. 5B. It is conceivable to form the through hole 160 as a result.

However, the resist layer R2 and the interlayer insulating layer 13
When the adhesiveness with 0 is poor, the etching liquid easily penetrates between the resist layer R2 and the interlayer insulating layer 130. Therefore, the etching rate in the lateral direction of the interlayer insulating layer 130 near the interface with the resist layer R2 becomes faster than in the vertical direction. Therefore, the lateral etching of the surface layer portion of the interlayer insulating layer 130 excessively proceeds, and the interlayer insulating layer 130 is etched.
There is a space between the resist and the central portion of the resist layer R2. Note that this is remarkable when the interlayer insulating layer 130 needs to be isotropically etched for a long time. When the resist layer R2 floats in this way, the resist layer R2 may peel off or the resist layer R2 may shift. If the resist layer R2 peels off or shifts, it becomes difficult to etch the region where the through hole is to be formed in the anisotropic etching process.
As a result, the yield is reduced.

5. Modification (1) In the above-described embodiment, the interlayer insulating layer 40 is composed of two layers. However, the present invention is not limited to this and may be composed of only one layer. In this case, the interlayer insulating layer 40 is B
It can be composed of only the PSG layer. This BPSG
The layer can be configured so that the concentration of boron becomes thinner toward the upper layer side. It should be noted that the lower the boron concentration, the faster the etching rate in etching using hydrofluoric acid as an etching solution, for example. According to this structure, as shown in FIG. 4, the diameter of the through hole 60 can be gradually reduced from top to bottom.

(2) In the above embodiment, an example of the combination of the BPSG layer 20 and the TEOS type silicon oxide layer 30 has been shown. However, the present invention is not limited to this, and the interlayer insulating layer 4
Any combination of materials may be used so that the upper insulating layer has a higher etching rate than the lower insulating layer in the side etching of 0.

For example, the interlayer insulating layer 40 is composed of two layers of BP.
It can also be composed of an SG layer. In this case, B above
The boron concentration of the PSG layer may be lower than the boron concentration of the lower BPSG layer. As a result, the etching rate of the upper BPSG layer becomes higher than that of the lower BPSG layer in the side etching process. Further, when forming such an interlayer insulating layer 40, the upper BPSG layer and the lower BPSG layer may be simultaneously reflowed at high temperature, or the lower BPSG layer may be reflowed at high temperature and then the upper BPSG layer is reflowed. Forming a BP on top
The SG layer can be hot reflowed.

(3) The interlayer insulating layer 40 may be formed by laminating three or more insulating layers. In this case, in the side etching step, a material that can increase the etching rate as the insulating layer is formed is selected.

(4) The interlayer insulating layer 40 may form a first interlayer insulating layer (for example, an interlayer insulating layer for insulating the gate electrode and the wiring layer provided thereon). The second and higher interlayer insulating layers may be formed. The method of the above-described embodiment is particularly useful when the interlayer insulating layer 40 constitutes the first interlayer insulating layer.
This is because the formation density of through holes in the first interlayer insulating layer is high.

(5) In the above-described embodiment, the interlayer insulating layer 40 in the through hole 60 is side-etched with the resist layer R1 formed. However, the invention is not limited to this, and the interlayer insulating layer 40 in the through hole 60 may be side-etched after removing the resist layer R1.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device according to an embodiment.

FIG. 2 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 3 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 4 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device according to a modification.

FIG. 5 is a cross-sectional view schematically showing a problem with a comparative example.

[Explanation of symbols]

10 Base 12 wiring layers 20 BPSG layer 30 TEOS-based silicon oxide layer 40 Interlayer insulation layer 60 through holes 62 Top of through hole 64 Lower part of through hole 70 Contact layer

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F033 JJ08 JJ09 JJ11 JJ12 JJ19                       KK00 NN31 PP06 PP14 PP26                       QQ09 QQ10 QQ12 QQ13 QQ16                       QQ21 QQ31 QQ33 QQ35 QQ37                       QQ74 QQ75 RR04 RR15 SS01                       SS02 SS04 SS11 SS15 XX02                 5F058 BA20 BD01 BD02 BD04 BF02                       BF07 BJ05

Claims (9)

[Claims] 1. A step of forming a first insulating layer,
(B) forming a second insulating layer on the first insulating layer, (c) forming a mask layer having a predetermined pattern on the second insulating layer, (d) the mask Etching the first insulating layer and the second insulating layer using the layer as a mask to form a through hole, and (e) side etching the first insulating layer and the second insulating layer in the through hole. And the step (e) is performed under the condition that the etching rate of the second insulating layer is faster than the etching rate of the first insulating layer. 2. The first insulating layer according to claim 1, wherein the first insulating layer is a silicon oxide layer containing boron and phosphorus, and the second insulating layer is obtained by reacting an organic silane compound with a compound containing oxygen. Formed silicon oxide layer,
Manufacturing method of semiconductor device. 3. (a) a step of forming an interlayer insulating layer,
(B) forming a mask layer having a predetermined pattern on the interlayer insulating layer, (c) etching the interlayer insulating layer using the mask layer as a mask to form a through hole, and (D) including a step of side-etching the interlayer insulating layer in the through hole, wherein in the step (d), an etching rate of an upper portion of the interlayer insulating layer is faster than an etching rate of a lower portion of the interlayer insulating layer. A method for manufacturing a semiconductor device, which is performed. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the interlayer insulating layer is composed of a silicon oxide layer containing boron and phosphorus, and the concentration of boron in the silicon oxide layer is thinner on the upper layer side than on the lower layer side. . 5. The interlayer insulating layer according to claim 3, wherein the interlayer insulating layer is formed by stacking a plurality of insulating layers, and the step (d) is performed under a condition that an etching rate becomes higher toward an upper insulating layer. , A method of manufacturing a semiconductor device. 6. An interlayer insulating layer having a through hole, wherein the interlayer insulating layer is composed of a silicon oxide layer containing boron and phosphorus, and the boron concentration of the interlayer insulating layer is lower on the upper layer side than on the lower layer side. Semiconductor device. 7. The diameter of the through hole according to claim 6, wherein the upper layer side is larger than the lower layer side.
Semiconductor device. 8. An interlayer insulating layer having a through hole, wherein the interlayer insulating layer includes a first silicon oxide layer containing boron and phosphorus, and a boron and phosphorus layer provided on the first silicon oxide layer. And a second silicon oxide layer containing the second silicon oxide layer, the boron concentration of the second silicon oxide layer is
A semiconductor device having a boron concentration less than that of the silicon oxide layer of. 9. The semiconductor device according to claim 8, wherein the diameter of the through hole in the second silicon oxide layer is larger than the diameter of the through hole in the first silicon oxide layer.