JPH0554262B2 - - Google Patents

Info

Publication number
JPH0554262B2
JPH0554262B2 JP23333084A JP23333084A JPH0554262B2 JP H0554262 B2 JPH0554262 B2 JP H0554262B2 JP 23333084 A JP23333084 A JP 23333084A JP 23333084 A JP23333084 A JP 23333084A JP H0554262 B2 JPH0554262 B2 JP H0554262B2
Authority
JP
Japan
Prior art keywords
semiconductor wafer
wafer
adhesive sheet
adhesive layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23333084A
Other languages
English (en)
Other versions
JPS61112345A (ja
Inventor
Takashi Kimura
Toshihiro Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59233330A priority Critical patent/JPS61112345A/ja
Priority to DE8585114207T priority patent/DE3583111D1/de
Priority to EP85114207A priority patent/EP0182218B1/en
Publication of JPS61112345A publication Critical patent/JPS61112345A/ja
Priority to US07/015,585 priority patent/US4722130A/en
Publication of JPH0554262B2 publication Critical patent/JPH0554262B2/ja
Granted legal-status Critical Current

Links

Classifications

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D1/00—Working stone or stone-like materials, e.g. brick, concrete or glass, not provided for elsewhere; Machines, devices, tools therefor
    • B28D1/003—Multipurpose machines; Equipment therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0058—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
    • B28D5/0082—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material for supporting, holding, feeding, conveying or discharging work
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
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Description

【発明の詳細な説明】 ［発明の技術分野］ この発明は半導体装置の製造方法に関し、特
に、ダイシングからダイボンデイングに至る工程
において半導体ウエハの損傷を効果的に防止する
ことができるとともに前記工程において高い歩留
りを実現できる新規な製造方法に関するものであ
る。
［発明の技術的背景］ 半導体装置の製造工程は、よく知られているよ
うに、半導体ウエハに素子を形成するための素子
形成工程（いわゆるウエハ工程）と、素子形成終
了後の半導体ウエハを枡目状に切断分割して得ら
れた多数の半導体チツプをフレームやケースに実
装するための実装工程とから構成される。
従来、素子形成終了後の半導体ウエハをチツプ
に分割する場合、分割に先立つてまず該半導体ウ
エハの素子形成面の裏面を研削もしくはラツピン
グ等によつて一様に削除して該半導体ウエハの厚
みを低減させ、薄化した半導体ウエハの裏面にチ
ツプのマウント性をよくするため金属薄膜を蒸着
するなどの必要な加工を加えた後、スクライビン
グプローブやダイヤモンドホイールもしくはダイ
ヤモンドブレード等の超硬工具で該半導体ウエハ
の素子形成面に枡目状に多数の溝を切り込んで該
半導体ウエハを多数のチツプに分割していた。そ
して、このようにして得られたチツプはフレーム
等への実装工程において例えば絶縁性ペーストも
しくはAg含有導電性ペーストを用いてリードフ
レームに接着されていた。
［背景技術の問題点］ 従来、使用する半導体ウエハが強度の高いシリ
コン半導体ウエハであつて且つチツプの所望の厚
みが比較的厚かつたため、前記のごとき従来の分
割方法によつても半導体ウエハに亀裂や好ましく
ない割れが発生することは比較的少なかつたが、
シリコンよりも脆弱なGaAsウエハを前記従来方
法で処理すると、切断予定線以外の場所に亀裂や
割れが発生しやすいため、量産上問題となつてい
た。
また、最近では、シリコン半導体装置において
も回路集積度の大規模化とチツプ歩留りの一層の
向上とを目標として従来よりも一層大口径の半導
体ウエハを使用することが計画される一方、素子
の高密度化に伴つてチツプの放熱性を高めるとと
もにチツプの小型化を目的として従来よりも薄肉
のチツプを使用することが計画されているが、こ
のように半導体ウエハが薄肉化し且つ大口径化す
ると強度が比較的大きなシリコン半導体ウエハで
も前記従来の方法では非常に亀裂や割れが発生し
やすくなり、従つて歩留りが大幅に低下する恐れ
があつた。しかも、現用のチツプよりも薄肉のチ
ツプをリードフレーム上に滴下したペーストで接
着すると、チツプ厚さが小さいためチツプ接着時
にペーストがチツプ表面にまで這い上がつて素子
がペーストによつて短絡もしくは汚染されてしま
う恐れがあり、従つて前記のごとき従来のチツプ
接着方法を薄肉チツプに適用した場合、半導体装
置の製造歩留りや信頼性が大幅に低下する恐れが
あつた。
［発明の目的］ この発明の目的は、現用のシリコン半導体ウエ
ハよりも大口径のシリコン半導体ウエハを用いて
薄肉のチツプからなる半導体装置を製造する場合
や、GaAs半導体ウエハから半導体装置を製造す
る場合において、該ウエハの損傷を未然に防止す
ることができるとともにダイシングからダイボン
デイングに至る工程において高い歩留りを実現し
且つ信頼性の高い半導体装置を製造することので
きる新規な半導体装置製造方法を提供することで
ある。
［発明の概要］ この発明の半導体装置の製造方法は、素子形成
後のウエハ表面にダイアモンドブレードなどによ
つてダイシング線に沿つて所定の深さまで溝切り
をした後、研削などに対してウエハ強度をおぎな
う必要があれば、ウエハ表面に第一の片面粘着シ
ートを貼着して、該ウエハの裏面を研削もしくは
ラツピング等によつて削除し、更に該裏面にダイ
ボンド用接着層を形成し（金属薄膜を形成してダ
イボンド用接着層を形成することもある）、次い
で該ダイボンド用接着層の表面に第二の片面粘着
シートをを貼着するとともに該第一の片面粘着シ
ートを該ウエハ表面から剥離するもので、ウエハ
の各チツプは分離するが更に該第二の片面粘着シ
ートを展張させて該ウエハの各チツプ部分を互い
に隔離させるようにもできるのである。
この発明の製造方法においては、ラツピング面
ダイボンド用接着剤を塗布し半硬化のダイボンド
用接着層が形成されており、分割後の各チツプの
裏面には所定厚さのダイボンド用接着層が形成さ
れているので、次のダイボンデイング工程におい
てダイボンド用接着剤を適用した場合のようにダ
イボンド用接着層がチツプ表面に這い上ることな
くボンデイングを行うことができる。また、ウエ
ハが比較的厚い時にチツプ分割用溝切りが行われ
る一方、ウエハ裏面にラツピングやラツピング後
の加工を行う時には、該ウエハが第一の片面粘着
シートによつて必要に応じ補強されているため、
ウエハに亀裂や割れが入る恐れがない。その結
果、本願発明により、従来の製造方法における前
記問題点が解決される。
［発明の実施例］ 以下に添付図面の第１図Ａ乃至Ｅを参照して本
発明方法の一実施例について説明する。
本発明の方法の実施するには、まず第一工程と
して第１図Ａに示すように素子形成を終了した厚
さ400μｍの半導体ウエハ１の素子形成面に公知
の方法で縦横に枡目状に深さ140μｍの溝１ａを
切り込んで該ウエハをハーフカツト状態又は全カ
ツトに近い状態にする。
次に第二工程として該半導体ウエハ１の素子形
成面（溝切り面）に第１図Ｂに示すように第一の
片面粘着シート２を貼りつける。なお、全カツト
状態に近く溝形成をするときは、第１図Ａの半導
体ウエハ１の裏面をあらかじめ補強片面粘着シー
ト（図示せず）で補強して溝切りをするのがよ
く、表面に第一の片面粘着シート２を貼り付けた
後に該補強片面粘着シートを除去すればよい。つ
いで第三工程として片面粘着シート２を貼着した
半導体ウエハ１の裏面をダイヤモンドホイール３
等で全面にわたつて研削し、ウエハが所定の
160μｍの厚さになるまで削除する。この研削量
の場合にはチツプは分離されていないが、分離で
きる厚さまで研削してもよい。
チツプ裏面に高周波素子にとつて必要な金属薄
膜などの蒸着法によつて形成する場合には、ウエ
ハを第一の片面粘着シートで補強した状態で蒸着
を行うことができる。
次にダイボンド接着層を形成するときは、スク
リーン印刷法を用いるか或いはその他の適当な方
法によつてエポキシ樹脂含有のペーストを半導体
ウエハ１の裏面全体にわたつて一様な厚さに塗布
した後、温度80℃で１時間程度のベーキングを行
うことにより、第１図Ｃに示すように半導体ウエ
ハ１の裏面に厚さ15μｍ程のＢステージ状態のダ
イボンド用接着層４を形成する（ダイボンド用接
着層４の形成に用いるペーストは絶縁性のもので
も導電性のものでもよいが、後者はチツプ裏面か
ら電極を取り出す形式のデバイスを製造する時に
使用するとよい）。
しかる後、第四工程として、第１図Ｄに示すよ
うにダイボンド用接着層４の下面に第二の片面粘
着シート５を貼りつけるとともに上面側の第一の
片面粘着シート２を剥離する。この場合、片面粘
着シート２を一方の側から順に剥離していくこと
により半導体ウエハ１の上向きの曲げモーメント
が作用するため溝１ａの底面部に亀裂１ｂが入
り、その結果、それまでは各溝１ａで互いに表面
側のみが分離されていた各チツプが完全に分離さ
れる。
第一の片面粘着シート２を剥離した後、第五工
程は第１図Ｅに示すように片面粘着シート５を矢
印ｆの方向に加熱して伸展するが、各チツプ１
Ａ，１Ｂ，…１Ｅの間の溝１ａも広がり、次のダ
イボンデイング工程においてチツプのピツクアツ
プが容易になる（なお、片面粘着シート５を加熱
せずに矢印方向の張力を加えて伸展させてもよ
い）。
ダイボンデイング工程においては、第二の片面
粘着シート５上から各チツプ１Ａ〜１Ｅをピツク
アツプしてダイボンデイングを行うが、各チツプ
の下面には予め半硬化されたダイボンド用接着層
４が形成されているので直ちにダイボンデイング
を行うことができ、しかも、各チツプ下面のダイ
ボンド用接着層４の厚さは予め厳密に制御されて
いるため、ダイボンデイング時に接着剤の這い上
がりが生ずることはない。
なお、第一及び第二の片面粘着シートの代り
に、片面粘着シートと接着力が異なる、平坦で剥
離性がよい塗膜を使用してもよく、またウエハ裏
面の研削加工としては、ダイヤモンドホイールに
よる研削のほか、ラツピング、ケミカルエツチン
グ等の方法もある。
［発明の効果］ 以上に説明したように、本発明の方法では、半
導体ウエハの裏面削除加工に先立つて素子形成面
に所定の深さの溝を形成した所望により第一の片
面粘着シートを貼りつけて補強を行うため、該ウ
エハの裏面削除加工時に半導体ウエハに亀裂を生
じる恐れがなく、その結果、大口径且つ薄肉の半
導体ウエハのダイシングも該ウエハに損傷を与え
ることなく行うことができる。
また、本発明方法では、ダイシング工程すなわ
ちウエハ分解工程においてダイボンド用接着層を
形成し、かつダイボンド用接着層の厚さを精密に
制御するのに好適であり、従つてダイボンデイン
グ時にダイボンデイング用接着剤がチツプ上面に
這い上がつてくる恐れがなく、ダイボンデイング
不良に基因する歩留り低下を生ずる恐れがない。
従つて、本発明の方法によれば、非常に大口径
且つ薄肉のシリコン半導体ウエハや脆いGaAsウ
エハから信頼性の高い半導体装置を高い製造歩留
りで製造することができ、本発明の方法はこれら
の半導体ウエハを使用する半導体装置のための量
産化技術として寄与するものである。
【図面の簡単な説明】
第１図のＡ乃至Ｅは本発明方法の工程を説明す
るための半導体ウエハの断面図である。 １……半導体ウエハ、２……第一の片面粘着シ
ート、３……ダイヤモンドホイール、４……ダイ
ヤボンド用接着層、５……第二の片面粘着シー
ト、１ａ……溝、１Ａ〜１Ｅ……チツプ。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体ウエハを各チツプ毎にダイシングする
    工程として、素子形成後の半導体ウエハの表面に
    格子状の溝を所定の深さまで形成する工程と、該
    溝を形成した後に、該半導体ウエハの裏面全面を
    所定の厚さだけ削除する工程と、該所定の厚さだ
    け裏面を削除した後の該半導体ウエハの裏面にダ
    イボンデイング時完全硬化するように半硬化状態
    のダイボンド用接着層を形成する工程と、該半導
    体ウエハのダイボンド用接着層面に片面粘着シー
    トを貼着する工程とを含む半導体装置の製造方
    法。 ２ 半導体ウエハの裏面全面を所定の厚さだけ削
    除する工程が、該溝を形成した表面の全面を片面
    粘着シートなどの補強材で補強した後になされる
    とともに、ダイボンド用接着層面に片面粘着シー
    トを貼着する工程の際に、片面粘着シートなどの
    補強材を該半導体基板の表面から除去する特許請
    求の範囲第１項記載の半導体装置の製造方法。 ３ 所定の厚さだけ裏面を削除した後の該半導体
    ウエハの裏面と、該ダイボンド用接着層との間
    に、金属薄膜を形成する工程を、さらに含む特許
    請求の範囲第１項又は第２項記載の半導体装置の
    製造方法。
JP59233330A 1984-11-07 1984-11-07 半導体装置の製造方法 Granted JPS61112345A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP59233330A JPS61112345A (ja) 1984-11-07 1984-11-07 半導体装置の製造方法
DE8585114207T DE3583111D1 (de) 1984-11-07 1985-11-07 Verfahren zum schneiden von halbleiterscheiben.
EP85114207A EP0182218B1 (en) 1984-11-07 1985-11-07 Method for dicing semiconductor wafer
US07/015,585 US4722130A (en) 1984-11-07 1987-02-17 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59233330A JPS61112345A (ja) 1984-11-07 1984-11-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS61112345A JPS61112345A (ja) 1986-05-30
JPH0554262B2 true JPH0554262B2 (ja) 1993-08-12

Family

ID=16953451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59233330A Granted JPS61112345A (ja) 1984-11-07 1984-11-07 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US4722130A (ja)
EP (1) EP0182218B1 (ja)
JP (1) JPS61112345A (ja)
DE (1) DE3583111D1 (ja)

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JPS61112345A (ja) 1986-05-30
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US4722130A (en) 1988-02-02
EP0182218A2 (en) 1986-05-28
EP0182218B1 (en) 1991-06-05

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